![](http://datasheet.mmic.net.cn/230000/79RC32438-200BB_datasheet_15568909/79RC32438-200BB_490.png)
IDT EJTAG System
EJTAG Processor Core Extensions
79RC32438 User Reference Manual
20 - 24
November 4, 2002
Notes
DERET Instruction
Format:
DERET
MIPS32 / MIPS64
Purpose:
Return from debug exception
Description:
The DERET instruction returns from Debug Mode and resumes non-debug execution at the instruction
pointed to by the DEPC register. DERET does not execute the next instruction (it has no delay slot).
Restrictions:
This instruction is legal only if the processor is executing in Debug Mode, and the DERET instruction is
not placed in a delay slot of a branch or a jump instruction. If the DERET instruction is executed in User
Mode when the StatusCU0 bit is cleared, then a Coprocessor Unusable exception occurs. If the DERET
instruction is executed in other circumstances including if placed in the delay slot of a branch or a jump
instruction when the processor is executing in Debug Mode, then operation of the processor is UNDE-
FINED.
If the DEPC register with the return address for DERET was modified by an MTC0/DMTC0 instruction,
then it must be followed by an appropriate spacing (refer to section “CP0 and dseg Hazards” on page 20-
12) before a DERET instruction in order to remove CP0 hazards. DERET implements a software barrier for
all changes in the CP0 state that could affect the fetch and decode of the instruction at the PC to which the
DERET returns, such as changes to the effective ASID, user-mode state, and addressing mode.
Operation:
if (DebugDM = 1) then
DebugDM ¨ 0
DebugIEXI ¨ 0
PC ¨ DEPC
elseif (in User Mode) and (SRCU0 = 0) then
InitiateCoprocessorUnusableException(0)
else
UNDEFINED
endif
Exceptions:
Coprocessor Unusable exception.
EJTAG Coprocessor 0 Registers
The Coprocessor 0 registers for EJTAG are shown in Table 20.15. Each register is described in more
detail in the following subsections.
Debug Exception Return
DERET
31
0
6
1
19
COP0
0 1 0 0 0 0
CO
1
24
26
25
DERET
0 1 1 1 1 1
0
6
6
5
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0