x
82801BA ICH2
Datasheet
5.16.3 Data Encoding and Bit Stuffing....................................................5-109
5.16.4 Bus Protocol ................................................................................5-110
5.16.4.1 Bit Ordering ..................................................................5-110
5.16.4.2 SYNC Field...................................................................5-110
5.16.4.3 Packet Field Formats ...................................................5-110
5.16.4.4 Address Fields..............................................................5-111
5.16.4.5 Frame Number Field ....................................................5-112
5.16.4.6 Data Field.....................................................................5-112
5.16.4.7 Cyclic Redundancy Check (CRC) ................................5-112
5.16.5 Packet Formats............................................................................5-113
5.16.5.1 Token Packets..............................................................5-113
5.16.5.2 Start of Frame Packets.................................................5-113
5.16.5.3 Data Packets................................................................5-114
5.16.5.4 Handshake Packets .....................................................5-114
5.16.5.5 Handshake Responses ................................................5-115
5.16.6 USB Interrupts .............................................................................5-115
5.16.6.1 Transaction Based Interrupts.......................................5-115
5.16.6.2 Non-Transaction Based Interrupts ...............................5-117
5.16.7 USB Power Management ............................................................5-117
5.16.8 USB Legacy Keyboard Operation................................................5-118
SMBus Controller Functional Description (D31:F3)..................................5-120
5.17.1 Host Controller.............................................................................5-120
5.17.1.1 Command Protocols.....................................................5-121
5.17.1.2 I
2
C Behavior.................................................................5-126
5.17.1.3 Heartbeat for Use With the External LAN Controller....5-126
5.17.2 Bus Arbitration .............................................................................5-127
5.17.3 Interrupts / SMI# ..........................................................................5-127
5.17.4 SMBALERT# ...............................................................................5-128
5.17.5 SMBus Slave Interface ................................................................5-128
AC’97 Controller Functional Description
(Audio D31:F5, Modem D31:F6)...............................................................5-132
5.18.1 AC-link Overview .........................................................................5-133
5.18.2 AC-Link Low Power Mode ...........................................................5-141
5.18.3 AC‘97 Cold Reset ........................................................................5-142
5.18.4 AC‘97 Warm Reset......................................................................5-142
5.18.5 System Reset ..............................................................................5-143
Firmware Hub Interface ............................................................................5-144
5.19.1 Field Definitions ...........................................................................5-144
5.19.2 Protocol........................................................................................5-145
5.17
5.18
5.19
6
Register and Memory Mapping..................................................................................6-1
6.1
PCI Devices and Functions ..........................................................................6-1
6.2
PCI Configuration Map .................................................................................6-2
6.3
I/O Map.........................................................................................................6-2
6.3.1
Fixed I/O Address Ranges...............................................................6-3
6.3.2
Variable I/O Decode Ranges...........................................................6-5
6.4
Memory Map.................................................................................................6-6
6.4.1
Boot-Block Update Scheme.............................................................6-7
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