82801BA ICH2
Datasheet
xix
14.1.13 SID—Subsystem ID (Modem—D31:F6) ........................................14-6
14.1.14 INTR_LN—Interrupt Line Register (Modem—D31:F6)..................14-6
14.1.15 INT_PIN—Interrupt Pin (Modem—D31:F6) ...................................14-6
AC’97 Modem I/O Space (D31:F6).............................................................14-7
14.2.1 x_BDBAR—Buffer Descriptor List Base Address Register............14-8
14.2.2 x_CIV—Current Index Value Register ...........................................14-9
14.2.3 x_LVI—Last Valid Index Register..................................................14-9
14.2.4 x_SR—Status Register................................................................14-10
14.2.5 x_PICB—Position In Current Buffer Register ..............................14-11
14.2.6 x_PIV—Prefetch Index Value Register........................................14-11
14.2.7 x_CR—Control Register ..............................................................14-11
14.2.8 GLOB_CNT—Global Control Register.........................................14-12
14.2.9 GLOB_STA—Global Status Register ..........................................14-13
14.2.10 CAS—Codec Access Semaphore Register.................................14-14
14.2
15
Pinout and Package Information..............................................................................15-1
15.1
Pinout..........................................................................................................15-1
15.2
Package Information...................................................................................15-9
16
Electrical Characteristics..........................................................................................16-1
16.1
Absolute Maximum Ratings........................................................................16-1
16.2
Functional Operating Range.......................................................................16-1
16.3
D.C. Characteristics....................................................................................16-2
16.4
A.C. Characteristics....................................................................................16-7
16.5
Timing Diagrams.......................................................................................16-16
17
Testability.................................................................................................................17-1
17.1
Test Mode Description................................................................................17-1
17.2
Tri-state Mode.............................................................................................17-2
17.3
XOR Chain Mode........................................................................................17-2
17.3.1 XOR Chain Testability Algorithm Example ....................................17-2
17.3.1.1 Test Pattern Consideration for XOR Chain 4 .................17-3
A
I/O Register Index..................................................................................................... A-1
B
Register Bit Index...................................................................................................... B-1
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