Intel
82801BA ICH2 Datasheet
A-9
I/O Register Index
Block Data Byte
07h
Section 12.2.7, “BLOCK_DB—Block Data Byte
Register” on page 12-9
Receive Slave Address
09h
Section 12.2.8, “RCV_SLVA—Receive Slave Address
Register” on page 12-9
Receive Slave Data
0Ah
Section 12.2.9, “SLV_DATA—Receive Slave Data
Register” on page 12-9
AC’97 Audio I/O Registers at NAMBAR + Offset
NAMBAR is set at Section 13.1.11, “NABMBAR—Native Audio Bus Mastering Base Address Register
(Audio—D31:F5)” on page 13-5
PCM In Buffer Descriptor list Base
Address Register
00h
Section 13.2.1, “x_BDBAR—Buffer Descriptor Base
Address Register” on page 13-9
PCM In Current Index Value
04h
Section 13.2.2, “x_CIV—Current Index Value
Register” on page 13-10
PCM In Last Valid Index
05h
Section 13.2.3, “x_LVI—Last Valid Index Register” on
page 13-10
PCM In Status Register
06h
Section 13.2.4, “x_SR—Status Register” on
page 13-11
PCM In Position In Current Buffer
08h
Section 13.2.5, “x_PICB—Position In Current Buffer
Register” on page 13-12
PCM In Prefetched Index Value
0Ah
Section 13.2.6, “x_PIV—Prefetched Index Value
Register” on page 13-12
PCM In Control Register
0Bh
Section 13.2.7, “x_CR—Control Register” on
page 13-13
PCM Out Buffer Descriptor list Base
Address Register
10h
Section 13.2.1, “x_BDBAR—Buffer Descriptor Base
Address Register” on page 13-9
PCM Out Current Index Value
14h
Section 13.2.2, “x_CIV—Current Index Value
Register” on page 13-10
PCM Out Last Valid Index
15h
Section 13.2.3, “x_LVI—Last Valid Index Register” on
page 13-10
PCM Out Status Register
16h
Section 13.2.4, “x_SR—Status Register” on
page 13-11
PCM Out Position In Current Buffer
18h
Section 13.2.5, “x_PICB—Position In Current Buffer
Register” on page 13-12
PCM Out Prefetched Index Value
1Ah
Section 13.2.6, “x_PIV—Prefetched Index Value
Register” on page 13-12
PCM Out Control Register
1Bh
Section 13.2.7, “x_CR—Control Register” on
page 13-13
Mic. In Buffer Descriptor list Base
Address Register
20h
Section 13.2.1, “x_BDBAR—Buffer Descriptor Base
Address Register” on page 13-9
Mic. In Current Index Value
24h
Section 13.2.2, “x_CIV—Current Index Value
Register” on page 13-10
Mic. In Last Valid Index
25h
Section 13.2.3, “x_LVI—Last Valid Index Register” on
page 13-10
Mic. In Status Register
26h
Section 13.2.4, “x_SR—Status Register” on
page 13-11
Mic In Position In Current Buffer
28h
Section 13.2.5, “x_PICB—Position In Current Buffer
Register” on page 13-12
Mic. In Prefetched Index Value
2Ah
Section 13.2.6, “x_PIV—Prefetched Index Value
Register” on page 13-12
Mic. In Control Register
2Bh
Section 13.2.7, “x_CR—Control Register” on
page 13-13
Table A-2. ICH2 Variable I/O Registers (Continued)
Register Name
Offset
EDS Section and Location
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