Intel
82801BA ICH2 Datasheet
A-7
I/O Register Index
SMI# Control and Enable
30–31h
Section 9.8.3.11, “SMI_EN—SMI Control and Enable
Register” on page 9-68
SMI Status Register
34–35h
Section 9.8.3.12, “SMI_STS—SMI Status Register”
on page 9-70
Monitor SMI Status
40h
Section 9.8.3.13, “MON_SMI—Device Monitor SMI
Status and Enable Register” on page 9-71
Device Activity Status
44h
Section 9.8.3.14, “DEVACT_STS—Device Activity
Status Register” on page 9-72
Device Trap Enable
48h
Section 9.8.3.15, “DEVTRAP_EN—Device Trap
Enable Register” on page 9-73
Bus Address Tracker
4Ch
Section 9.8.3.16, “BUS_ADDR_TRACK—Bus
Address Tracker Register” on page 9-74
Bus Cycle Tracker
4Eh
Section 9.8.3.17, “BUS_CYC_TRACK—Bus Cycle
Tracker Register” on page 9-74
TCO I/O Registers at TCOBASE + Offset
TCOBASE = PMBASE + 40h
PMBASE is set in Section 9.1.10, “PMBASE—ACPI Base Address (LPC I/F—D31:F0)” on page 9-6
TCO_RLD: TCO Timer Reload and
Current Value
00h
Section 9.9.2, “TCO1_RLD—TCO Timer Reload and
Current Value Register” on page 9-75
TCO_TMR: TCO Timer Initial Value
01h
Section 9.9.3, “TCO1_TMR—TCO Timer Initial Value
Register” on page 9-76
TCO_DAT_IN: TCO Data In
02h
Section 9.9.4, “TCO1_DAT_IN—TCO Data In
Register” on page 9-76
TCO_DAT_OUT: TCO Data Out
03h
Section 9.9.5, “TCO1_DAT_OUT—TCO Data Out
Register” on page 9-76
TCO1_STS: TCO Status
04h–05h
Section 9.9.6, “TCO1_STS—TCO1 Status Register”
on page 9-76
TCO2_STS: TCO Status
06h–07h
Section 9.9.7, “TCO2_STS—TCO2 Status Register”
on page 9-78
TCO1_CNT: TCO Control
08h–09h
Section 9.9.8, “TCO1_CNT—TCO1 Control Register”
on page 9-79
TCO2_CNT: TCO Control
0Ah–0Bh
Section 9.9.9, “TCO2_CNT—TCO2 Control Register”
on page 9-80
GPIO I/O Registers at GPIOBASE + Offset
GPIOBASE is set in Section 9.1.14, “GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)” on page 9-8
GPIO Use Select
00–03h
Section 9.10.2, “GPIO_USE_SEL—GPIO Use Select
Register” on page 9-83
GPIO Input/Output Select
04–07h
Section 9.10.3, “GP_IO_SEL—GPIO Input/Output
Select Register” on page 9-84
GPIO Level for Input or Output
0C–0Fh
Section 9.10.4, “GP_LVL—GPIO Level for Input or
Output Register” on page 9-84
GPIO Blink Enable
18–1Bh
Section 9.10.5, “GPO_BLINK—GPO Blink Enable
Register” on page 9-85
GPIO Signal Invert
2C–2Fh
Section 9.10.6, “GPI_INV—GPIO Signal Invert
Register” on page 9-86
Table A-2. ICH2 Variable I/O Registers (Continued)
Register Name
Offset
EDS Section and Location
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