Intel
82801BA ICH2 Datasheet
2-9
Signal Description
2.12
SMBus Interface
2.13
System Management Interface
RCIN#
I
Keyboard Controller Reset Processor:
The keyboard controller can generate
INIT# to the processor. This saves the external OR gate with the ICH2’s other
sources of INIT#. When the ICH2 detects the assertion of this signal, INIT# is
generated for 16 PCI clocks.
Note that the ICH2 ignores RCIN# assertion during transitions to the S3, S4 and
S5 states.
A20GATE
I
A20 Gate:
This signal is from the keyboard controller. It acts as an alternative
method to force the A20M# signal active. A20GATE saves the external OR gate
needed with various other PCIsets.
CPUPWRGD
OD
Processor Power Good:
This signal should be connected to the processor’s
PWRGOOD input. This is an open-drain output signal (external pull-up resistor
required) that represents a logical AND of the ICH2’s PWROK and VRMPWRGD
signals.
Table 2-12. SM Bus Interface Signals
Name
Type
Description
SMBDATA
I/OD
SMBus Data:
External pull-up is required.
SMBCLK
I/OD
SMBus Clock:
External pull-up is required.
SMBALERT#
/
GPIO[11]
I
SMBus Alert:
This signal is used to wake the system or generate an SMI#. If not
used for SMBALERT#, it can be used as a GPI.
Table 2-13. System Management Interface Signals
Name
Type
Description
INTRUDER#
I
Intruder Detect:
This signal can be set to disable system if box detected open.
This signal’s status is readable, so it can be used like a GPI if the Intruder
Detection is not needed.
SMLINK[1:0]
I/OD
System Management Link:
These signals are an SMBus link to an optional
external system management ASIC or LAN controller. External pull-ups are
required.
Note that SMLINK[0] corresponds to an SMBus Clock signal and SMLINK[1]
corresponds to an SMBus Data signal.
Table 2-11. Processor Interface Signals (Continued)
Name
Type
Description
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