Intel
82801BA ICH2 Datasheet
5-75
Functional Description
NOTES:
1. This will be a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP
bits via software.
It is important to understand that the various GPIs have different levels of functionality when used
as wake events. The GPIs that reside in the core power well can only generate wake events from an
S1 state. Also, only certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits
reside in ACPI I/O space.
Table 5-44
summarizes the use of GPIs as wake events.
The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply
design. Approximations are shown in
Table 5-45
. The time indicates from when the Wake event
occurs (signal transition) to when the processor is allowed to start its first cycle (CPURST# goes
inactive). There will be very large additional delays for the processor to execute sufficient amounts
of BIOS to invoke the OS (such as coming out of S1–S3) or spinning up the hard drive
(e.g., coming out of S4 or S5).
PME#
S1
–
S5
(Note 1)
Set PME_EN bit in GPE0_EN Register.
GST Timeout
S1M
Setting the GST Timeout range to a value other than 00h.
SMBALERT#
S1
–
S4
S1
–
S5
SMB_WAK_EN in the GPE0 Register
SMBus Slave Message
Always enabled as a Wake Event
Table 5-43. Causes of Wake Events (Continued)
Cause
States Can
Wake From
How Enabled
Table 5-44. GPI Wake Events
GPI
Power Well
Wake From
Notes
GPI[7:0], GPI[23:16]
Core
S1
GPI[15:8]
Resume
S1
–
S5
ACPI Compliant
Table 5-45. Sleep State Exit Latencies
State
Latency
S1
<1 ms. Based on wake event to STPCLK# high + re-enumeration of PCI bus, USB, CardBus, etc.
Must also add PLL spin-up times.
S3
Power Supply ramp + 20 ms
S4
Power Supply ramp + 20 ms
S5
Power Supply ramp + 20 ms
Powered by ICminer.com Electronic-Library Service CopyRight 2003