Signal Description
2-2
Intel
82801BA ICH2 Datasheet
2.3
EEPROM Interface
2.4
Firmware Hub Interface
2.5
PCI Interface
Table 2-3. EEPROM Interface Signals
Name
Type
Description
EE_SHCLK
O
EEPROM Shift Clock
: EE_SHCLK is the serial shift clock output to the EEPROM.
EE_DIN
I
EEPROM Data In
: EE_DIN transfers data from the EEPROM to the ICH2. This
signal has an integrated pull-up resistor.
EE_DOUT
O
EEPROM Data Out
: EE_DOUT transfers data from the ICH2 to the EEPROM.
EE_CS
O
EEPROM Chip Select
: EE_CS is a chip-select signal to the EEPROM.
Table 2-4. Firmware Hub Interface Signals
Name
Type
Description
FWH[3:0]
/
LAD[3:0]
I/O
Firmware Hub Signals.
These signals are muxed with LPC address signals.
FWH[4]
/
LFRAME#
I/O
Firmware Hub Signals.
This signal is muxed with LPC LFRAME# signal.
Table 2-5. PCI Interface Signals
Name
Type
Description
AD[31:0]
I/O
PCI Address/Data:
AD[31:0] is a multiplexed address and data bus. During the first
clock of a transaction, AD[31:0] contain a physical address (32 bits). During
subsequent clocks, AD[31:0] contain data. The ICH2 drives all 0s on AD[31:0]
during the address phase of all PCI Special Cycles.
C/BE[3:0]#
I/O
Bus Command and Byte Enables:
The command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the
Byte Enables.
C/BE[3:0]#
Command Type
0000
Interrupt Acknowledge
0001
Special Cycle
0010
I/O Read
0011
I/O Write
0110
Memory Read
0111
Memory Write
1010
Configuration Read
1011
Configuration Write
1100
Memory Read Multiple
1110
Memory Read Line
1111
Memory Write and Invalidate
All command encodings not shown are reserved. The ICH2 does not decode
reserved values, and therefore will not respond if a PCI master generates a cycle
using one of the reserved values.
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