Intel
82801BA ICH2 Datasheet
14-7
AC’97 Modem Controller Registers (D31:F6)
14.2
AC’97 Modem I/O Space (D31:F6)
In the case of the split codec implementation accesses to the modem mixer registers in different
codecs are differentiated by the controller by using address offsets 00h–7Fh for the primary codec
and address offsets 80h–FEh for the secondary codec.
Table 14-2
shows the register addresses for
the modem mixer registers.
NOTE:
1. Registers in bold are multiplexed between audio and modem functions
2. Registers in italics are for functions not supported by the ICH2
3. Software should not try to access reserved registers
4. The ICH2 supports a modem codec as either primary or secondary, but does not support two modem codecs.
The Global Control (GLOB_CNT) and Global Status (GLOB_STA) registers are aliased to the
same global registers in the audio and modem I/O space. Therefore a read/write to these registers in
either audio or modem I/O space affects the same physical register.
These registers exist in I/O space and reside in the AC ‘97 controller. The two channels, Modem in
and Modem out, each have their own set of Bus Mastering registers. The following register
descriptions apply to both channels. The naming prefix convention used is as follows:
MI = Modem in channel
MO = Modem out channel
Table 14-2. ICH2 Modem Mixer Register Configuration
Register
MMBAR Exposed Registers (D31:F6)
Primary
Secondary
Name
00h:38h
80h:B8h
Intel RESERVED
3Ch
BCh
Extended Modem ID
3Eh
BEh
Extended Modem Status/Control
40h
C0h
Line 1 DAC/ADC Rate
Line 2 DAC/ADC Rate
2
Handset DAC/ADC Rate
2
42h
C2h
44h
C4h
46h
C6h
Line 1 DAC/ADC Level Mute
Line 2 DAC/ADC Level Mute
2
Handset DAC/ADC Level Mute
2
48h
C8h
4Ah
CAh
4Ch
CCh
GPIO Pin Configuration
4Eh
CEh
GPIO Polarity/Type
50h
D0h
GPIO Pin Sticky
52h
D2h
GPIO Pin Wake Up
54h
D4h
GPIO Pin Status
56h
58h
1
7Ah
1
7Ch
1
7Eh
1
D6h
Misc. Modem AFE Stat/Ctrl
D8h
Vendor Reserved
FAh
Vendor Reserved
FCh
Vendor ID1
FEh
Vendor ID2
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