SMBus Controller Registers (D31:F3)
12-4
Intel
82801BA ICH2 Datasheet
12.1.9
SID—Subsystem ID (SMBUS—D31:F2/F4)
Address Offset:
Default Value:
Lockable:
2Eh–2Fh
00h
No
Attribute:
Size:
Power Well:
RO
16 bits
Core
12.1.10
INTR_LN—Interrupt Line Register (SMBUS—D31:F3)
Address Offset:
Default Value:
3Ch
00h
Attributes:
Size:
R/W
8 bits
12.1.11
INTR_PN—Interrupt Pin Register (SMBUS—D31:F3)
Address Offset:
Default Value:
3Dh
02h
Attributes:
Size:
RO
8 bits
12.1.12
HOSTC—Host Configuration Register (SMBUS—D31:F3)
Address Offset:
Default Value:
40h
00h
Attribute:
Size:
R/W
8 bits
Bit
Description
15:0
Subsystem ID (SID)—
R/Write-Once. The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems from each other. The value returned
by reads to this register is the same as that which was written by BIOS into the IDE_SID register.
Bit
Description
7:0
Interrupt line—
R/W.
This data is not used by the ICH2. It is to communicate to software the interrupt
line that the interrupt pin is connected to PIRQB#.
Bit
Description
7:0
Interrupt PIN—
RO.
02h =
Indicates that the ICH2 SMBus Controller will drive PIRQB# as its interrupt line.
Bit
Description
7:3
Reserved.
2
I
2
C Enable (I2C_EN)—
R/W.
0 = SMBus behavior.
1 = The ICH2 is enabled to communicate with I
2
C devices. This will change the formatting of some
commands.
1
SMBus to SMI Enable (SMB_SMI_EN)—
R/W.
0 = SMBus interrupts will not generate an SMI#.
1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. This bit will only
take effect if the INTREN bit is set in I/O space.This bit needs to be set for SMBALERT# to be
enabled.
0
SMBus Host Enable (HST_EN)
—R/W.
0 = Disable the SMBus Host Controller.
1 = Enable. The SMB Host Controller interface is enabled to execute commands. The INTREN bit
needs to be enabled for the SMB Host Controller to interrupt or SMI#. Note that the SMB Host
Controller will not respond to any new requests until all interrupt requests have been serviced.
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