參數(shù)資料
型號: ADSP-21489KSWZ-4B
廠商: Analog Devices Inc
文件頁數(shù): 26/68頁
文件大?。?/td> 0K
描述: IC CCD SIGNAL PROCESSOR 176LQFP
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: EBI/EMI,DAI,I²C,SPI,SPORT,UART/USART
時鐘速率: 400MHz
非易失內(nèi)存: 外部
芯片上RAM: 5Mb
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.10V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-LQFP 裸露焊盤
供應商設備封裝: 176-LQFP-EP(24x24)
包裝: 托盤
Rev. B
|
Page 32 of 68
|
March 2013
SDRAM Interface Timing (166 MHz SDCLK)
The maximum frequency for SDRAM is 166 MHz. For informa-
tion on SDRAM frequency and programming, see the
ADSP-214xx SHARC Processor Hardware Reference, Engineer-
to-Engineer Note “Interfacing SDRAM Memories to SHARC
Processors” (EE-286), and the SDRAM vendor data sheet.
Table 31. SDRAM Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSDAT
DATA Setup Before SDCLK
0.7
ns
tHSDAT
DATA Hold After SDCLK
1.23
ns
Switching Characteristics
tSDCLK
1
SDCLK Period
6
ns
tSDCLKH
SDCLK Width High
2.2
ns
tSDCLKL
SDCLK Width Low
2.2
ns
tDCAD
2
Command, ADDR, Data Delay After SDCLK
4
ns
tHCAD
Command, ADDR, Data Hold After SDCLK
1
ns
tDSDAT
Data Disable After SDCLK
5.3
ns
tENSDAT
Data Enable After SDCLK
0.3
ns
1 Systems should use the SDRAM model with a speed grade higher than the desired SDRAM controller speed. For example, to run the SDRAM controller at 166 MHz the
SDRAM model with a speed grade of 183 MHz or above should be used. See Engineer-to-Engineer Note “Interfacing SDRAM Memories to SHARC Processors” (EE-286) for
more information on hardware design guidelines for the SDRAM interface.
2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.
Figure 18. SDRAM Interface Timing
SDCLK
DATA (IN)
DATA (OUT)
COMMAND/ADDR
(OUT)
tSDCLKH
tSDCLKL
tHSDAT
tSSDAT
tHCAD
tDCAD
tENSDAT
tDCAD
tDSDAT
tHCAD
tSDCLK
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