參數(shù)資料
型號(hào): ADSP-21489KSWZ-4B
廠商: Analog Devices Inc
文件頁數(shù): 44/68頁
文件大?。?/td> 0K
描述: IC CCD SIGNAL PROCESSOR 176LQFP
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: EBI/EMI,DAI,I²C,SPI,SPORT,UART/USART
時(shí)鐘速率: 400MHz
非易失內(nèi)存: 外部
芯片上RAM: 5Mb
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.10V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 176-LQFP-EP(24x24)
包裝: 托盤
Rev. B
|
Page 49 of 68
|
March 2013
SPI Interface—Master
The ADSP-2148x contains two SPI ports. Both primary and sec-
ondary are available through DPI only. The timing provided in
Table 50 and Table 51 applies to both.
Table 50. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Min
Max
Unit
Timing Requirements
tSSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time)
8.2
ns
tHSPIDM
SPICLK Last Sampling Edge to Data Input Not Valid
2
ns
Switching Characteristics
tSPICLKM
Serial Clock Cycle
8 × tPCLK – 2
ns
tSPICHM
Serial Clock High Period
4 × tPCLK – 2
ns
tSPICLM
Serial Clock Low Period
4 × tPCLK – 2
ns
tDDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time)
2.5
ns
tHDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
4 × tPCLK – 2
ns
tSDSCIM
DPI Pin (SPI Device Select) Low to First SPICLK Edge
4 × tPCLK – 2
ns
tHDSM
Last SPICLK Edge to DPI Pin (SPI Device Select) High
4 × tPCLK – 2
ns
tSPITDM
Sequential Transfer Delay
4 × tPCLK – 1.2
ns
Figure 35. SPI Master Timing
tSPICHM
tSDSCIM
tSPICLM
tSPICLKM
tHDSM
tSPITDM
tDDSPIDM
tHSPIDM
tSSPIDM
DPI
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
CPHASE = 1
CPHASE = 0
tHDSPIDM
tHSPIDM
tSSPIDM
tDDSPIDM
tHDSPIDM
SPICLK
(CP = 0,
CP = 1)
(OUTPUT)
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