- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19468 > ADSP-21489KSWZ-4B (Analog Devices Inc)IC CCD SIGNAL PROCESSOR 176LQFP PDF資料下載
參數(shù)資料
| 型號： | ADSP-21489KSWZ-4B |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/68頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 176LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | EBI/EMI，DAI，I²C，SPI，SPORT，UART/USART |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.10V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 176-LQFP-EP（24x24） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
Rev. B
|
Page 17 of 68
|
March 2013
CLK_CFG1–0
I
Core to CLKIN Ratio Control. These pins set the start up clock frequency.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset. The
allowed values are:
00 = 8:1
01 = 32:1
10 = 16:1
11 = reserved
CLKIN
I
Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures
the processors to use either its internal clock generator or an external clock source.
Connecting the necessary components to CLKIN and XTAL enables the internal clock
generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the processors to use the external clock source such as an external clock
oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.
XTAL
O
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
RESET
I
Processor Reset. Resets the processor to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
RESETOUT/
RUNRSTIN
I/O (ipu)
Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also
has a second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL
register. For more information, see the ADSP-214xx SHARC Processor Hardware Reference.
BOOT_CFG2–0
I
Boot Configuration Select. These pins select the boot mode for the processor (see
Table 9). The BOOT_CFG pins must be valid before RESET (hardware and software) is
asserted.
1 The MLB pins are only available on the automotive models.
Table 12. Pin List, Power and Ground
Name
Type
Description
VDD_INT
P
Internal Power Supply
VDD_EXT
P
I/O Power Supply
GND1
G
Ground
VDD_THD
P
Thermal Diode Power Supply. When not used, this pin can be left floating.
1 The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the
exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. No separate GND pins are provided
in the package.
Table 11. Pin Descriptions (Continued)
Name
Type
State
During/
After Reset
Description
The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot
be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The
range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical
conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MEV3S0515SC | CONV DC/DC 3W 5V IN 15V OUT SIP |
| HSM28DSAI | CONN EDGECARD 56POS R/A .156 SLD |
| MAX31855NASA+T | IC CONV THERMOCOUPLE-DGTL 8SOIC |
| ADSP-2189MKSTZ-300 | IC DSP CONTROLLER 16BIT 100-LQFP |
| VI-B1N-CX-B1 | CONVERTER MOD DC/DC 18.5V 75W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21489KSWZ-5B | 制造商:Analog Devices 功能描述:450 MHZ SHARC W/ STATIC VOLTAG 制造商:Analog Devices 功能描述:450 MHZ SHARC W/ STATIC VOLTAGE SCALING - Trays 制造商:Analog Devices 功能描述:Digital Signal Processors & Controllers - DSP, DSC High Perf 4th Generation 制造商:Analog Devices 功能描述:450 MHz SHARC w/ Static Voltage Scaling |
| ADSP-21489KSWZENGA | 制造商:Analog Devices 功能描述:SHARC PROCESSOR - Trays |
| ADSP-21532S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ADSP-21532S: Blackfin? DSP Preliminary Data Sheet (Rev. PrD. 3/03) |
| ADSP21532SBBCENG | 制造商:Analog Devices 功能描述: |
| ADSP-21532SBCA-300 | 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。