參數(shù)資料
型號(hào)： ADSP-21489KSWZ-4B
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 66/68頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 176LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類(lèi)型： 浮點(diǎn)
接口： EBI/EMI，DAI，I²C，SPI，SPORT，UART/USART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： 外部
芯片上RAM： 5Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.10V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 176-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 176-LQFP-EP（24x24）
包裝： 托盤(pán)
Rev. B
|
Page 7 of 68
|
March 2013
instruction that retrieves 48-bit memory. The 32-bit section
describes what this address range looks like to an instruction
that retrieves 32-bit memory.
ROM Based Security
The ADSP-2148x has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code. When using this
feature, the processor does not boot-load any external code, exe-
cuting exclusively from internal ROM. Additionally, the
processor is not freely accessible via the JTAG port. Instead, a
unique 64-bit key, which must be scanned in through the JTAG
or Test Access Port will be assigned to each customer. The
device will ignore a wrong key. Emulation features are available
after the correct key is scanned.
On-Chip Memory Bandwidth
The internal memory architecture allows programs to have four
accesses at the same time to any of the four blocks (assuming
there are no block conflicts). The total bandwidth is realized
using the DMD and PMD buses (2 × 64-bits, CCLK speed) and
the IOD0/1 buses (2 × 32-bit, PCLK speed).
FAMILY PERIPHERAL ARCHITECTURE
The ADSP-2148x family contains a rich set of peripherals that
support a wide variety of applications including high quality
audio, medical imaging, communications, military, test equip-
ment, 3D graphics, speech recognition, motor control, imaging,
and other applications.
External Memory
The external port interface supports access to the external mem-
ory through core and DMA accesses. The external memory
address space is divided into four banks. Any bank can be pro-
grammed as either asynchronous or synchronous memory. The
external ports are comprised of the following modules.
An Asynchronous Memory Interface which communicates
with SRAM, FLASH, and other devices that meet the stan-
dard asynchronous SRAM access protocol. The AMI
supports 6M words of external memory in bank 0 and 8M
words of external memory in bank 1, bank 2, and bank 3.
A SDRAM controller that supports a glueless interface with
any of the standard SDRAMs. The SDC supports 62M
words of external memory in bank 0, and 64M words of
external memory in bank 1, bank 2, and bank 3. NOTE: this
feature is not available on the ADSP-21486 product.
Table 4. Internal Memory Space (5 MBits—ADSP-21486/ADSP-21487/ADSP-21489)1
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 Bits)
Extended Precision Normal or
Instruction Word (48 Bits)
Normal Word (32 Bits)
Short Word (16 Bits)
Block 0 ROM (Reserved)
0x0004 0000–0x0004 7FFF
Block 0 ROM (Reserved)
0x0008 0000–0x0008 AAA9
Block 0 ROM (Reserved)
0x0008 0000–0x0008 FFFF
Block 0 ROM (Reserved)
0x0010 0000–0x0011 FFFF
Reserved
0x0004 8000–0x0004 8FFF
Reserved
0x0008 AAAA–0x0008 BFFF
Reserved
0x0009 0000–0x0009 1FFF
Reserved
0x0012 0000–0x0012 3FFF
Block 0 SRAM
0x0004 9000–0x0004 EFFF
Block 0 SRAM
0x0008 C000–0x0009 3FFF
Block 0 SRAM
0x0009 2000–0x0009 DFFF
Block 0 SRAM
0x0012 4000–0x0013 BFFF
Reserved
0x0004 F000–0x0004 FFFF
Reserved
0x0009 4000–0x0009 FFFF
Reserved
0x0009 E000–0x0009 FFFF
Reserved
0x0013 C000–0x0013 FFFF
Block 1 ROM (Reserved)
0x0005 0000–0x0005 7FFF
Block 1 ROM (Reserved)
0x000A 0000–0x000A AAA9
Block 1 ROM (Reserved)
0x000A 0000–0x000A FFFF
Block 1 ROM (Reserved)
0x0014 0000–0x0015 FFFF
Reserved
0x0005 8000–0x0005 8FFF
Reserved
0x000A AAAA–0x000A BFFF
Reserved
0x000B 0000–0x000B 1FFF
Reserved
0x0016 0000–0x0016 3FFF
Block 1 SRAM
0x0005 9000–0x0005 EFFF
Block 1 SRAM
0x000A C000–0x000B 3FFF
Block 1 SRAM
0x000B 2000–0x000B DFFF
Block 1 SRAM
0x0016 4000–0x0017 BFFF
Reserved
0x0005 F000–0x0005 FFFF
Reserved
0x000B 4000–0x000B FFFF
Reserved
0x000B E000–0x000B FFFF
Reserved
0x0017 C000–0x0017 FFFF
Block 2 SRAM
0x0006 0000–0x0006 3FFF
Block 2 SRAM
0x000C 0000–0x000C 5554
Block 2 SRAM
0x000C 0000–0x000C 7FFF
Block 2 SRAM
0x0018 0000–0x0018 FFFF
Reserved
0x0006 4000– 0x0006 FFFF
Reserved
0x000C 5555–0x000D FFFF
Reserved
0x000C 8000–0x000D FFFF
Reserved
0x0019 0000–0x001B FFFF
Block 3 SRAM
0x0007 0000–0x0007 3FFF
Block 3 SRAM
0x000E 0000–0x000E 5554
Block 3 SRAM
0x000E 0000–0x000E 7FFF
Block 3 SRAM
0x001C 0000–0x001C FFFF
Reserved
0x0007 4000–0x0007 FFFF
Reserved
0x000E 5555–0x0000F FFFF
Reserved
0x000E 8000–0x000F FFFF
Reserved
0x001D 0000–0x001F FFFF
1 Some ADSP-2148x processors include a customer-definable ROM block and are not reserved as shown on this table. Please contact your Analog Devices sales representative
for additional details.
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