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參數資料
| 型號： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設備的DSP1620/27/28/29 O控制注冊說明 |
| 文件頁數： | 11/114頁 |
| 文件大小： | 804K |
| 代理商： | DSP1620 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
9
4 Hardware Architecture
(continued)
Bit Manipulation Unit (BMU)
The BMU extends the DSP1600 core instruction set to
provide more efficient bit operations on accumulators.
The BMU contains logic for barrel shifting, normaliza-
tion, and bit field insertion/extraction. The unit also con-
tains a set of 36-bit alternate accumulators. The data in
the alternate accumulators can be shuffled with the data
in the main accumulators. Flags returned by the BMU
mesh seamlessly with the DSP1600 conditional instruc-
tions.
Error Correction Coprocessor (ECCP)
The ECCP performs full Viterbi decoding with instruc-
tions for MLSE equalization and convolutional decod-
ing. It is designed for 2-tap to 6-tap MLSE equalization
with Euclidean branch metrics and rate 1/1 to 1/6 con-
volutional decoding using constraint lengths from 2 to 7
with Euclidean or Manhattan branch metrics. Two vari-
ants of soft-decoded symbols, as well as hard-decoded
symbols may be programmed. The ECCP operates in
parallel with the DSP1600 core, increasing the through-
put rate. Single instruction Viterbi decoding provides
significant code compression required for single DSP
solutions in modern digital cellular applications. The
ECCP is the source of two interrupts and one flag to the
DSP1600 core.
Bit Input/Output (BIO)
The BIO provides convenient and efficient monitoring
and control of eight individually configurable pins. When
configured as outputs, the pins can be individually set,
cleared, or toggled. When configured as inputs, individ-
ual pins or combinations of pins can be tested for pat-
terns. Flags returned by the BIO mesh seamlessly with
conditional instructions.
Serial Input/Output Units (SIO and SIO2)
SIO and SIO2 offer asynchronous, full-duplex, double-
buffered channels that operate at up to 25 Mbits/s (for
20 ns instruction cycle in a nonmultiprocessor configu-
ration), and easily interface with other Lucent Technol-
ogies fixed-point DSPs in a multiple-processor
environment. Commercially available codecs and time-
division multiplex (TDM) channels can be interfaced to
the serial I/O ports with few, if any, additional compo-
nents. SIO2 is identical to SIO.
An 8-bit serial protocol channel may be transmitted in
addition to the address of the called processor in multi-
processor mode. This feature is useful for transmitting
high-level framing information or for error detection and
correction. SIO2 and BIO are pin-multiplexed with the
PHIF.
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| DSP1627F32K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
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