- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄377000 > DSP1620 TVS 400W 6.0V BIDIRECT SMA PDF資料下載
參數(shù)資料
| 型號(hào)： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說(shuō)明 |
| 文件頁(yè)數(shù)： | 39/114頁(yè) |
| 文件大小： | 804K |
| 代理商： | DSP1620 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)當(dāng)前第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
37
4 Hardware Architecture
(continued)
The frequency of the PLL output clock, f
VCO
, is deter-
mined by the values loaded into the 3-bit N divider and
the 5-bit M divider. When the PLL is selected and
locked, the frequency of the internal processor clock is
related to the frequency of CKI by the following equa-
tions:
f
VCO
= f
CKI
* M/N
f
INTERNAL CLOCK
= f
CKO
= f
VCO
÷
2
The frequency of the VCO, f
VCO
, must fall within the
range listed in Table 63. Also note that f
VCO
must be at
least twice f
CKI
.
The coding of the Mbits and Nbits is described as fol-
lows:
Mbits = M
2
if (N = 1)
Nbits = 0x7
else
Nbits = N
2
where N ranges from 1 to 8 and M ranges from 2 to 20.
The loop filter bits LF[3:0] should be programmed ac-
cording to Table 64.
Two other bits in the
pllc
register control the PLL. Clear-
ing the PLLEN bit powers down the PLL; setting this bit
powers up the PLL. Clearing the PLLSEL bit deselects
the PLL so that the DSP is clocked by a 1X version of
the CKI input; setting the PLLSEL bit selects the PLL-
generated clock for the source of the DSP internal pro-
cessor clock. The
pllc
register is cleared on reset and
powerup. Therefore, the DSP comes out of reset with
the PLL deselected and powered down. M and N should
be changed only while the PLL is deselected. The val-
ues of M and N should not be changed when powering
down or deselecting the PLL.
As previously mentioned, the PLL also provides a user
flag, LOCK, to indicate when the loop has locked. When
this flag is not asserted, the PLL output is unstable. The
DSP should not be switched to the PLL-based clock
without first checking that the lock flag is set. The lock
flag is cleared by writing to the
pllc
register. When the
PLL is deselected, it is necessary to wait for the PLL to
relock before the DSP can be switched to the PLL-
based clock. Before the input clock is stopped, the PLL
should be powered down. Otherwise, the LOCK flag will
not be reset and there may be no way to determine if the
PLL is stable, once the input clock is applied again.
The lock-in time depends on the frequency of operation
and the values programmed for M and N (see Table 64).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP1628 | TVS 400W 60V BIDIRECT SMA |
| DSP16210 | TVS 400W 6.5V UNIDIRECT SMA |
| DSP1627 | TVS 400W 6.5V BIDIRECT SMA |
| DSP1629 | TVS 400W 64V UNIDIRECT SMA |
| DSP16410C | TVS 400W 7.0V UNIDIRECT SMA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP16210 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:DSP16210 Digital Signal Processor |
| DSP1627 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:DSP1627 Digital Signal Processor |
| DSP1627F32K10IR | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K10IT | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11I | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:16-Bit Digital Signal Processor |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。