參數(shù)資料
型號: DSP1620
英文描述: TVS 400W 6.0V BIDIRECT SMA
中文描述: 澄清,串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明
文件頁數(shù): 62/114頁
文件大?。?/td> 804K
代理商: DSP1620
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
60
Lucent Technologies Inc.
5 Software Architecture
(continued)
Table 35. timerc Register
Bit
Field
15—7
Reserved
6
5
4
3—0
DISABLE
RELOAD
T0EN
PRESCALE
Field
DISABLE
Value
0
1
Description
Timer enabled.
Timer and prescaler disabled. The period register and
timer0
are
not reset.
Timer stops after counting down to 0.
Timer automatically reloads and repeats indefinitely.
Timer holds current count.
Timer counts down to 0.
See table below.
RELOAD
0
1
0
1
T0EN
PRESCALE
PRESCALE Field
PRESCALE
0000
0001
0010
0011
0100
0101
0110
0111
Frequency of
Timer Interrupts
CKO/2
CKO/4
CKO/8
CKO/16
CKO/32
CKO/64
CKO/128
CKO/256
PRESCALE
1000
1001
1010
1011
1100
1101
1110
1111
Frequency of
Timer Interrupts
CKO/512
CKO/1024
CKO/2048
CKO/4096
CKO/8192
CKO/16384
CKO/32768
CKO/65536
Table 36. Phase-Locked Loop Control (pllc) Register
Bit
Field
15
14
13
ICP
12
11—8
LF[3:0]
7—5
Nbits[2:0]
4—0
PLLEN
PLLSEL
Reserved
Mbits[4:0]
Field
PLLEN
Value
0
1
0
1
0
Description
PLL powered down.
PLL powered up.
DSP internal clock taken directly from CKI.
DSP internal clock taken from PLL.
Charge pump current selection (see Table 64 for proper value).
Loop filter setting (see Table 64 for proper value).
Encodes N, 1
N
8, where N = Nbits[2:0] + 2, unless Nbits[2:0] = 111, then N = 1.
Encodes M, 2
M
20, where M = Mbits[4:0] + 2, f
INTERNAL CLOCK
= f
CKI
x (M/(2N)).
PLLSEL
ICP
Reserved
LF[3:0]
Nbits[2:0]
Mbits[4:0]
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