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參數(shù)資料
| 型號： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明 |
| 文件頁數(shù)： | 48/114頁 |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1620 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
46
Lucent Technologies Inc.
5 Software Architecture
5.1 Instruction Set
The DSP1628 processor has seven types of instruc-
tions: multiply/ALU, special function, control, F3 ALU,
BMU, cache, and data move. The multiply/ALU instruc-
tions are the primary instructions used to implement sig-
nal processing algorithms. Statements from this group
can be combined to generate multiply/accumulate, log-
ical, and other ALU functions and to transfer data be-
tween memory and registers in the data arithmetic unit.
The special function instructions can be conditionally
executed based on flags from the previous ALU or BMU
operation, the condition of one of the counters, or the
value of a pseudorandom bit in the DSP1628 device.
Special function instructions perform shift, round, and
complement functions. The F3 ALU instructions enrich
the operations available on accumulators. The BMU in-
structions provide high-performance bit manipulation.
The control instructions implement the goto and call
commands. Control instructions can also be executed
conditionally. Cache instructions are used to implement
low-overhead loops, conserve program memory, and
decrease the execution time of certain multiply/ALU in-
structions. Data move instructions are used to transfer
data between memory and registers or between accu-
mulators and registers. See the DSP1611/17/18/27
Digital Signal Processor Information Manual or a de-
tailed description of the instruction set.
The following operators are used in describing the in-
struction set:
*
16 x 16-bit –> 32-bit multiplication
or
register-in-
direct addressing when used as a prefix to an ad-
dress register
or
denotes direct addressing when
used as a prefix to an immediate
+
36-bit addition
–
36-bit subtraction
>>
Arithmetic right shift
>>>
Logical right shift
<<
Arithmetic left shift
<<<
Logical left shift
|
36-bit bitwise OR
&
36-bit bitwise AND
^
36-bit bitwise EXCLUSIVE OR
:
Compound address swapping, accumulator
shuffling
~
One's complement
These are 36-bit operations. One operand is 36-bit data in an accu-
mulator; the other operand may be 16, 32, or 36 bits.
Object Code Compatibility
The DSP1628 is object code compatible with the
DSP1618 with the following exceptions:
I
ECCP user flag, EBUSY, which indicates error
correction coprocessor activity, has changed its
condition field.
The EBUSY flag is used in conjunction with the
if CON F2
or
if CON
goto/call/return
instructions
to monitor the ECCP operation. The object code
corresponding to
ifc EBUSY
, for example, must be
modified to reflect the change in condition codes.
Alternately, the source code can be assembled using
DSP1628 development tools.
I
The SIO and SIO2 interrupts (IBF, IBF2, OBE, and
OBE2) are cleared one instruction cycle AFTER
reading or writing the serial data registers, (
sdx
[in],
sdx2
[in],
sdx
[out], or
sdx2
[out]). To account for this
added latency, the user must ensure that a single
instruction (NOP or any other valid DSP16XX
instruction) follows the
sdx
register read or write
instruction prior to exiting an interrupt service routine
(via an ireturn or goto pi instruction) or before check-
ing the
ins
register for the SIO flag status. Adding
this instruction ensures that interrupts are not
reported incorrectly following an ireturn or that stale
flags are not read from the
ins
register. Refer to
TECHNICAL ADVISORY #23.
Multiply/ALU Instructions
Note that the function statements and transfer state-
ments in Table 17 are chosen independently. Any func-
tion statement (F1) can be combined with any transfer
statement to form a valid multiply/ALU instruction. If ei-
ther statement is not required, a single statement from
either column also constitutes a valid instruction. The
number of cycles to execute the instruction is a function
of the transfer column. (An instruction with no transfer
statement executes in one instruction cycle.) Whenever
PC,
pt
, or
rM
is used in the instruction and points to ex-
ternal memory, the programmed number of wait-states
must be added to the instruction cycle count. All multi-
ply/ALU instructions require one word of program mem-
ory. The no-operation (
nop
) instruction is a special case
encoding of a multiply/ALU instruction and executes in
one cycle. The assembly-language representation of a
nop
is either
nop
or a single semicolon.
Condition
DSP1618
ebusy
reserved
CON
11100
11101
DSP1628
lock
ebusy
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| DSP1627F32K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
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