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參數(shù)資料
| 型號(hào)： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說(shuō)明 |
| 文件頁(yè)數(shù)： | 40/114頁(yè) |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1620 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
38
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
PLL Programming Examples
The following section of code illustrates how the PLL would be initialized on powerup, assuming the following oper-
ating conditions:
CKI input frequency = 10 MHz
Internal clock and CKO frequency = 50 MHz
VCO frequency = 100 MHz
Input divide down count N = 2 (Set
Nbits[2:0]
= 000 to get N = 2, as described in Table 36.)
Feedback down count M = 20 (Set
Mbits[4:0]
= 10010 to get M = 18 + 2 = 20, as described in Table 36.)
The device would come out of reset with the PLL disabled and deselected.
pllinit:
pllc
= 0x2912
pllc
= 0xA912 /* Power on PLL, but PLL remains deselected */
call pllwait
/* Loop to check for LOCK flag assertion */
pllc
= 0xE912 /* Select high-speed, PLL clock */
goto start
/* User's code, now running at 50 MHz */
pllwait: if lock return
goto pllwait
/* Running CKI input clock at 10 MHz, set up counters in PLL */
Programming examples which illustrate how to use the PLL with the various power management modes are listed
in Section 4.14.
Latency
The switch between the CKI-based clock and the PLL-based clock is synchronous. This method results in the actual
switch taking place several cycles after the PLLSEL bit is changed. During this time, actual code can be executed,
but it will be at the previous clock rate. Table 16 shows the latency times for switching between CKI-based and PLL-
based clocks. In the example given, the delay to switch to the PLL source is 1—4 CKO cycles and to switch back is
11—31 CKO cycles.
Frequency Accuracy and Jitter
When using the PLL to multiply the input clock frequency up to the instruction clock rate, it is important to realize
that although the average frequency of the internal clock and CKO will have about the same relative accuracy as
the input clock, noise sources within the DSP will produce jitter on the PLL clock such that each individual clock
period will have some error associated with it. The PLL is guaranteed only to have sufficiently low jitter to operate
the DSP, and thus, this clock should not be used as an input to jitter-sensitive devices in the system.
V
DDA
and V
SSA
Connections
The PLL has its own power and ground pins, V
DDA
and V
SSA
. Additional filtering should be provided for V
DDA
in the
form of a ferrite bead connected from V
DDA
to V
DD
and two decoupling capacitors (4.7
μ
F tantalum in parallel with
a 0.01
μ
F ceramic) from V
DDA
to V
SS
. V
SSA
can be connected directly to the main ground plane. This recommen-
dation is subject to change and may need to be modified for specific applications depending on the characteristics
of the supply noise.
Note
: For devices with the CMOS clock input option, the CKI2 pin should be connected to V
SSA
.
Table 16. Latency Times for Switching Between CKI and PLL-Based Clocks
Minimum
Latency (cycles)
Maximum
Latency (cycles)
Switch to PLL-based clock
1
N + 2
Switch from PLL-based clock
M/N + 1
M + M/N + 1
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