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參數(shù)資料
| 型號： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明 |
| 文件頁數(shù)： | 46/114頁 |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1620 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
44
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
Power Management Examples with the PLL
The following examples show the more significant options for reducing power dissipation if operation with the PLL
clock synthesizer is desired.
Standard Sleep Mode, PLL Running.
This mode would be entered in the same manner as without the PLL. While
the input to the clock synthesizer, CKI, remains running, the
alf
register's AWAIT bit is set. The PLL will continue to
run and dissipate power. Peripheral units may be turned off to further reduce the sleep power.
powerc
= 0x00F0
sleep:a0 = 0x8000
do 1 {
alf = a0
nop
}
nop
nop
cont: . . .
powerc
= 0x0
/* Turn off peripherals, core running with PLL */
/* Set alf register in cache loop if running from */
/* external memory with >1 wait state */
/* Stop internal processor clock, interrupt circuits */
/* active */
/* Needed for bedtime execution. Only sleep power plus PLL */
/* power consumed here.... Interrupt wakes up the device */
/* User code executes here */
/* Turn peripheral units back on */
Sleep with Slow Internal Clock, PLL Running
. In this case, the ring oscillator is selected to clock the processor
before the device is put to sleep. This will reduce power dissipation while waiting for an interrupt to continue program
execution.
powerc
= 0x40F0
2*nop
sleep:a0 = 0x8000
do 1 {
alf = a0
nop
}
nop
nop
/* Turn off peripherals and select slow clock */
/* Wait for slow clock to take effect */
/* Set alf register in cache loop if running from */
/* external memory with >1 wait state */
/* Stop internal processor clock, interrupt circuits */
/* active */
/* Needed for bedtime execution. Reduced sleep power, PLL */
/* power, and ring oscillator power consumed here... */
/* Interrupt wakes up the device */
/* User code executes here */
/* Select high-speed PLL based clock */
/* Wait for it to take effect */
/* Turn peripheral units back on */
cont: . . .
powerc
= 0x00F0
2*nop
powerc
= 0x0000
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| DSP1627 | TVS 400W 6.5V BIDIRECT SMA |
| DSP1629 | TVS 400W 64V UNIDIRECT SMA |
| DSP16410C | TVS 400W 7.0V UNIDIRECT SMA |
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| DSP1627 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP1627 Digital Signal Processor |
| DSP1627F32K10IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
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