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參數(shù)資料
| 型號： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明 |
| 文件頁數(shù)： | 87/114頁 |
| 文件大小： | 804K |
| 代理商： | DSP1620 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
85
Lucent Technologies Inc.
9 Electrical Characteristics and Requirements
(continued)
* T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).
t
L
= PLL lock time (see Table 64).
The power dissipation listed is for internal power dissipation only. Total power dissipation can be calculated on the
basis of the application by adding C x V
DD
2
x f for each output, where C is the additional load capacitance and f is
the output frequency.
Power dissipation due to the input buffers is highly dependent on the input voltage level. At full CMOS levels, es-
sentially no dc current is drawn. However, for levels between the power supply rails, especially at or near the thresh-
old of V
DD
/2, high currents can flow. Although input and I/O buffers may be left untied (since the input voltage levels
of the input and I/O buffers are designed to remain at full CMOS levels when not driven by the DSP), it is still rec-
ommended that unused input and I/O pins be tied to V
SS
or V
DD
through a 10 k
resistor to avoid application am-
biguities. Further, if I/O pins are tied high or low, they should be pulled fully to V
SS
or V
DD
.
WARNING: The device needs to be clocked for at least six CKI cycles during reset after powerup. Other-
wise, high currents may flow.
Table 65. Power Dissipation and Wake-Up Latency
(continued)
Operating Mode
(Unused inputs at V
DD
or V
SS)
Typical Power Dissipation (mW)
Wake-Up Latency
V
DD=
3 V
3 V
3 V
3 V
I/O Units ON, ECCP OFF
powerc[7:4,0] = 0x01
I/O Units OFF, ECCP OFF
powerc[7:4,0] = 0xF1
(PLL Not Used
During Wake State)
(PLL Used
During Wake State)
Sleep with Slow Internal Clock
Small Signal Disabled
powerc[15:14] = 11,
alf[15] = 1, ioc = 0x0180
PLL Disabled During Sleep
Small Signal
0.40
0.30
20
μ
s
20
μ
s + t
L
Software Stop
powerc[15:12] = 0011
PLL Disabled During STOP
CMOS
0.060
0.060
3T*
3T* + t
L
Software Stop
powerc[15:12] = 1111
PLL Disabled During STOP
Small Signal
0.060
0.060
20
μ
s
20
μ
s + t
L
Hardware Stop (STOP = V
SS
)
powerc[15:12] = 0000
PLL Disabled During STOP
CMOS
0.060
1.20
0.060
1.20
3T*
3T*
—
—
Small Signal
Hardware Stop (STOP = V
SS
)
powerc[15:12] = 0000
PLL Enabled During STOP
CMOS
2.5
3.6
2.5
3.6
3T*
3T*
3T*
3T*
Small Signal
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