參數(shù)資料
型號： DSP1620
英文描述： TVS 400W 6.0V BIDIRECT SMA
中文描述： 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明
文件頁數(shù)： 61/114頁
文件大?。?/td> 804K
代理商： DSP1620
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
59
5 Software Architecture
(continued)
* JINT is a JTAG interrupt and is controlled by the HDS. It may be made unmaskable by the Lucent Technologies development system tools.
Encoding: A 0 disables an interrupt; a 1 enables an interrupt.
Encoding: A 0 indicates no interrupt. A 1 indicates an interrupt has been recognized and is pending or being ser-
viced. If a 1 is written to bits 4, 5, 8, 12, or 13 of
ins
, the corresponding interrupt is cleared.
Table 32. Parallel Host Interface Control (phifc) Register
Bit
Field
15—7
Reserved
6
5
4
3
2
1
0
PSOBEF
PFLAGSEL
PFLAG
PBSELF
PSTRB
PSTROBE
PMODE
Field
PMODE
Value
0
1
0
1
0
1
0
1
Description
8-bit data transfers.
16-bit data transfers.
Intelprotocol: PIDS and PODS data strobes.
Motorolaprotocol: PRWN and PDS data strobes.
When PSTROBE = 1, PODS pin (PDS) active-low.
When PSTROBE = 1, PODS pin (PDS) active-high.
In either mode, PBSEL pin = 0 ->
pdx0
low byte. See Table 7.
If PMODE = 0, PBSEL pin = 1 ->
pdx0
low byte.
If PMODE = 1, PBSEL pin = 0 ->
pdx0
high byte.
PIBF and POBE pins active-high.
PIBF and POBE pins active-low.
Normal.
PIBF flag ORed with POBE flag and output on PIBF pin; POBE pin un-
changed (output buffer empty).
Normal.
POBE flag as read through PSTAT register is active-low.
PSTROBE
PSTRB
PBSELF
PFLAG
0
1
0
1
PFLAGSEL
PSOBEF
0
1
Table 33. Interrupt Control (inc) Register
Bit
Field
15
14
rsrvd
13
12
11
rsrvd
10
9
8
7—6
rsrvd
5—4
INT[1:0]
3
2
1
0
JINT*
EREADY
EOVF
OBE2
IBF2
TIME
PIBF
POBE
OBE
IBF
Table 34. Interrupt Status (ins) Register
Bit
Field
15
JINT
14
rsrvd
13
12
11
rsrvd
10
9
8
7—6
rsrvd
5—4
INT[1:0]
3
2
1
0
EREADY
EOVF
OBE2
IBF2
TIME
PIBF
POBE
OBE
IBF
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