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| 型號(hào)： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說(shuō)明 |
| 文件頁(yè)數(shù)： | 8/114頁(yè) |
| 文件大小： | 804K |
| 代理商： | DSP1620 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
6
Lucent Technologies Inc.
3 Pin Information
(continued)
Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions. The functionality of CKI and CKI2
pins are mask-programmable (see Section 7, Mask-Programmable Options). Input levels on all I and I/O type pins
are designed to remain at full CMOS levels when not driven by the DSP.
*
3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0, except CKO which is free-running.
Pull-up devices on input.
§
3-states by JTAG control.
** See Section 7, Mask-Programmable Options.
For SIO multiprocessor applications, add 5 k
external pull-up resistors to SADD1 and/or SADD2 for proper initialization.
3-states when RSTB = 0, or by JTAG control.
Table 1. Pin Descriptions
PBGA Pin
B6, A6, B5,
A5, B4, A4,
B3, A3, B2,
A2, A1, B1,
C2, C1, C3,
D1
D2
E1
BQFP Pin TQFP Pin
1, 2, 3, 4,
5, 7, 8, 9,
10, 11, 12,
15, 16, 17,
18, 19
Symbol
DB[15:0]
Type
I/O*
Name/Function
88, 89, 90,
91, 92, 94,
95, 96, 97,
98, 99, 2,
3, 4, 5, 6
External Memory Data Bus 15—0.
20
21
7
8
IO
O
O
Data Address 0x4000 to 0x40FF I/O Enable.
Data Address 0x8000 to 0xFFFF External RAM
Enable.
Data Address 0x4100 to 0x7FFF External RAM
Enable.
Program Address External ROM Enable.
ERAMHI
E2
23
10
ERAMLO
O
F1
24
11
EROM
O
O
I
O*
F2
G1
25
27
12
14
RWN
EXM
AB[15:0]
Read/Write Not.
External ROM Enable.
External Memory Address Bus 15—0.
G2, H1, H2,
J1, J2, K1,
K2, L1, L2,
M1, K3, M2,
L3, M3, L4,
M4
L5
M5
L6
M6
L7
M7
L8
M8
L9
M9
L10
28, 29, 31,
32, 33, 34,
35, 36, 37,
40, 41, 42,
43, 44, 45,
46
47
48
50
51
52
53
54
56
57
58
59
15, 16, 18,
19, 20, 21,
22, 23, 24,
27, 28, 29,
30, 31, 32,
33
34
35
37
38
39
40
41
43
44
45
46
INT1
INT0
IACK
STOP
TRAP
RSTB
CKO
TCK
TMS
TDO
TDI
I
I
Vectored Interrupt 1.
Vectored Interrupt 0.
Interrupt Acknowledge.
STOP Input Clock.
Nonmaskable Program Trap/Breakpoint Indication.
Reset Bar.
Processor Clock Output.
JTAG Test Clock.
JTAG Test Mode Select.
JTAG Test Data Output.
JTAG Test Data Input.
Mask-Programmable Input Clock Option
CMOS
CKI
V
SSA
Vectored Interrupt Indication 0/Status/Control Bit 7.
Vectored Interrupt Indication 1/Status/Control Bit 6.
Vectored Interrupt Indication 2/Status/Control Bit 5.
Vectored Interrupt Indication 3/Status/Control Bit 4.
Status/Control Bit 3/PHIF Data Bus Bit 7.
Status/Control Bit 2/PHIF Data Bus Bit 6.
O*
I
I/O*
I
O
I
I
O
§
I
Small Signal
VAC
VCM
L11
M11
K10
L12
K11
K12
J11
J12
61
62
65
66
67
68
69
70
48
49
52
53
54
55
56
57
CKI**
CKI2**
I
I
VEC0/IOBIT7
VEC1/IOBIT6
VEC2/IOBIT5
VEC3/IOBIT4
IOBIT3/PB7
IOBIT2/PB6
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
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