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參數(shù)資料
| 型號(hào)： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說明 |
| 文件頁數(shù)： | 35/114頁 |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1620 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
33
4 Hardware Architecture
(continued)
Table 13. Memory-Mapped Registers
(continued)
Address
Register
Register Bit Field
0x407
Received Symbol/Channel Tap Register
S1H1
Convolutional decoding case:
Bit 7:0 is reserved.
Bit 15:8 is S1.
MLSE equalization case:
Bit 7:0 is HQ1.
Bit 15:8 is HI1.
Convolutional decoding case:
Bit 7:0 is reserved.
Bit 15:8 is S0.
MLSE equalization case:
Bit 7:0 is HQ0.
Bit 15:8 is HI0.
Bit 7:0 is zero.
Bit 15:8 is decoded symbol.
Convolutional case:
Bit 7:0 is G0.
Bit 15:8 is G1.
MLSE case:
Bit 9:0 is in-phase part of received signal.
Bit 15:10 is reserved.
Convolutional case:
Bit 7:0 is G2.
Bit 15:8 is G3.
MLSE case:
Bit 9:0 is quadrature-phase part of received signal.
Bit 15:10 is reserved.
Convolutional case:
Bit 7:0 is G4.
Bit 15:8 is G5.
MLSE case:
Bit 15:0 is reserved.
Bit 7:0 is used.
Bit 15:8 is reserved.
0x040E
Bit 15:8 is zero.
Bit 7:0 is upper byte of the minimum accumulated cost 0x040F.
Bit 15:0 is the lower 2 bytes of the minimum accumulated cost.
Traceback shift register (TBSR)
Bit 7:0 TBSR.
Bit 15:8 is reserved.
Reserved.
0x408
Received Symbol/Channel Tap Register
S0H0
0x409
Decoded Symbol Register
DSR
Received Real Signal/Generating Polynomial
ZIG10
0x40a
0x40b
Received Imaginary Signal/Generating Polynomial
ZQG32
0x40c
Generating Polynomial
G54
0x40d
Minimum Cost Index Register
MIDX
Minimum Accumulated Cost Register
MACH
MACL
0x40e—f
0x410
Traceback Shift Register
TBSR
0x411—0x7FF
Reserved Registers
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