參數(shù)資料
型號: DSP1627
英文描述: TVS 400W 6.5V BIDIRECT SMA
中文描述: DSP1627數(shù)字信號處理器
文件頁數(shù): 117/154頁
文件大小: 2365K
代理商: DSP1627
Data Sheet
March 2000
DSP1627 Digital Signal Processor
Lucent Technologies Inc.
117
11 Timing Characteristics for 3.0 V Operation
(continued)
*
See sioc register, MSB field, to determine if B0 is the MSB or LSB. See sioc register, ILEN field, to determine if the DO word length is 8 bits
or 16 bits.
Figure 55. SIO Passive Mode Output Timing Diagram
Device is fully static; t80 is tested at 200 ns.
For multiprocessor mode, see note in Section 12.10.
Table 140. Timing Requirements for Serial Inputs
Abbreviated Reference
t80
t81
t82
t83
t84
t85
Parameter
Min
40
18
18
8
8
0
Max
Unit
ns
ns
ns
ns
ns
ns
Clock Period (high to high)
Clock Low Time (low to high)
Clock High Time (high to low)
Load High Setup (high to high)
Load Low Setup (low to high)
Load Hold (high to invalid)
Table 141. Timing Characteristics for Serial Outputs
Abbreviated Reference
t87
t88
t89
t90
t92
t93
t94
t95
t96
Parameter
Min
5
5
Max
35
35
35
35
35
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Delay (high to valid)
Enable Data Delay (low to active)
Disable Data Delay (high to 3-state)
Data Hold (high to invalid)
Address Delay (high to valid)
Address Hold (high to invalid)
Enable Delay (low to active)
Disable Delay (high to 3-state)
OBE Delay (high to high)
DOEN
V
IH
V
IL
SADD
V
OH
V
OL
OLD
V
IH
V
IL
OCK
V
IH
V
IL
t85
t80
t81
t82
t84
t83
t85
t88
B0
B1
B7
BN – 1
t90
t90
t87
t94
AD0
AD1
AD7
t93
t93
t92
AS7
t89
t95
OBE
V
OH
V
OL
DO*
V
OH
V
OL
t96
5-4796 (F)
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