
Data Sheet
March 2000
DSP1627 Digital Signal Processor
Lucent Technologies Inc.
135
12 Timing Characteristics for 2.7 V Operation
(continued)
Figure 73. PHIF MotorolaMode Signaling (Pulse Period and Flags) Timing Diagram
* An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. For example, t53 and t54 should be referenced to
PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first.
All requirements referenced to PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or
complete a transaction.
PDS is programmable to be active-high or active-low. It is shown active-low in Figures 72 and 73. POBE and PIBF may be programmed to
be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
Table 170. Timing Characteristics for PHIF Motorola Mode Signaling
Abbreviated Reference
t53*
t54*
Parameter
Min
—
—
Max
20
20
Unit
ns
ns
PCSN/PDS
to POBE
(high to high)
PCSN/PDS
to PIBF
(high to high)
Table 171. Timing Requirements for PHIF MotorolaMode Signaling
Abbreviated Reference
t55
t56
Parameter
Min
20
20
Max
—
—
Unit
ns
ns
PCSN/PDS/PRWN Pulse Width (high to low)
PCSN/PDS/PRWN Pulse Width (low to high)
PDS
PRWN
V
IH
–
V
IL
–
t55
t56
t55
t56
t55
t56
PCSN
t53
t54
16-bit READ
8-bit WRITE
PBSEL
POBE
PIBF
t54
t56
t56
t55
t53
8-bit READ
16-bit WRITE
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
OH
–
V
OL
–
V
OH
–
V
OL
–
V
OH
–
V
OL
–
5-4039 (F).a