參數(shù)資料
型號: DSP1627
英文描述: TVS 400W 6.5V BIDIRECT SMA
中文描述: DSP1627數(shù)字信號處理器
文件頁數(shù): 143/154頁
文件大?。?/td> 2365K
代理商: DSP1627
Data Sheet
March 2000
DSP1627 Digital Signal Processor
Lucent Technologies Inc.
143
12 Timing Characteristics for 2.7 V Operation
(continued)
12.10 Multiprocessor Communication
*
Negative edge initiates time slot 0.
Figure 82. SIO Multiprocessor Timing Diagram
Note:
All serial I/O timing requirements and characteristics still apply, but the minimum clock period in passive
multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2.
* With capacitance load on ICK, OCK, DO, SYNC, and SADD = 100 pF, add 4 ns to t116—t122.
Table 184. Timing Requirements for SIO Multiprocessor Communication
Abbreviated Reference
t112
t113
t114
t115
Parameter
Min
35
0
12
0
Max
Unit
ns
ns
ns
ns
Sync Setup (high/low to high)
Sync Hold (high to high/low)
Address Setup (valid to high)
Address Hold (high to invalid)
Table 185. Timing Characteristics for SIO Multiprocessor Communication
Abbreviated Reference*
t116
t117
t120
t121
t122
Parameter
Min
Max
35
30
25
35
30
Unit
ns
ns
ns
ns
ns
Data Delay (bit 0 only) (low to valid)
Data Disable Delay (high to 3-state)
DOEN Valid Delay (high to valid)
Address Delay (bit 0 only) (low to valid)
Address Disable Delay (high to 3-state)
OCK/ICK
B0
B15
B8
B7
B1
B0
B15
SYNC
V
IH
V
IL
DO/D1
V
OH
V
OL
DOEN
V
OH
V
OL
t112
t113
t112
t113
TIME SLOT 1
TIME SLOT 2
t117
t116
AD0
AS7
AS0
AD7
AD1
AD0
SADD
t122
t121
t114
t115
t120
t120
*
5-4799 (F)
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