參數(shù)資料
型號: DSP1627
英文描述: TVS 400W 6.5V BIDIRECT SMA
中文描述: DSP1627數(shù)字信號處理器
文件頁數(shù): 57/154頁
文件大小: 2365K
代理商: DSP1627
Data Sheet
March 2000
DSP1627 Digital Signal Processor
Lucent Technologies Inc.
57
5 Software Architecture
(continued)
Field Descriptions
Table 41. T Field
Specifies the type of instruction.
Table 42. D Field
Specifies a destination accumulator.
Table 43.
aT
Field
Specifies transfer accumulator.
Table 44. S Field
Specifies a source accumulator.
Table 45. F1 Field
Specifies the multiply/ALU function.
Table 46. X Field
Specifies the addressing of ROM data in two-operand
multiply/ALU instructions. Specifies the high or low half
of an accumulator or the
y
register in one-operand mul-
tiply/ALU instructions.
T
Operation
goto JA
Short imm j, k, rb, re
Short imm r0, r1, r2, r3
Y = a1[l]
Z : aT[l]
Y
aT[l] = Y
Bit 0 = 0, aT = R
Bit 0 = 1, aTl = R
Bit 10 = 0, R = a0
Bit 10 = 1, R = a0l
R = IM16
Bit 10 = 0, R = a1
Bit 10 = 1, R = a1l
Y = R
Z : R
do, redo
R = Y
call JA
ifc CON
if CON
Y = y[l]
Z : y[l]
x = Y
y[l] = Y
Bit 0 = 0, branch indirect
Bit 0 = 1, F3 ALU
y = a0 x = X
Cond. branch qualifier
y = a1 x = X
Y = a0[l]
Z : y x = X
Bit 5 = 0, F4 ALU (BMU)
Bit 5 = 1, direct addressing
y = Y x = X
Format
4
9
9
1
2a
1
1a
7
7
7
7
8
7
7
7
7
10
7
4
3
3
1
2
1
1
5
3a
1
6
1
1
2
3b
9a
1
0000x
00010
00011
00100
00101
00110
00111
01000
01000
01001
01001
01010
01011
01011
01100
01101
01110
01111
1000x
10010
10011
10100
10101
10110
10111
11000
11000
11001
11010
11011
11100
11101
11110
11110
11111
F1
F1
F1
F1
F2
F2
F1
F1
F1
F1
F1
F1
F1
F1
F1
D
0
1
Register
Accumulator 0
Accumulator 1
aT
0
1
Register
Accumulator 1
Accumulator 0
S
0
1
Register
Accumulator 0
Accumulator 1
F1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Operation
aD = pp = x * y
aD = aS + pp = x * y
p = x *
y
aD = aS – pp = x * y
aD = p
aD = aS + p
nop
aD = aS – p
aD = aS | y
aD = aS ^ y
aS & y
aS – y
aD = y
aD = aS + y
aD = aS & y
aD = aS – y
X
Operation
Two-Operand Multiply/ALU
0
*
pt++
*
pt++i
1
One-Operand Multiply/ALU
0
1
aTl, yl
aTh, yh
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