參數(shù)資料
型號(hào): DSP1627
英文描述: TVS 400W 6.5V BIDIRECT SMA
中文描述: DSP1627數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 24/154頁(yè)
文件大?。?/td> 2365K
代理商: DSP1627
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
24
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
The PRESCALE field of the timerc register selects one
of 16 possible clock rates for the timer input clock (see
Table 31, timerc Register).
Setting the DISABLE bit of the timerc register to a logic
1 shuts down the timer and the prescaler for power sav-
ings. Setting the TIMERDIS, bit 4, in the powerc register
has the same effect of shutting down the timer. The
DISABLE bit and the TIMERDIS bit are cleared by writ-
ing a 0 to their respective registers to restore the normal
operating mode.
4.11 JTAG Test Port
The DSP1627 uses a JTAG/IEEE1149.1 standard four-
wire test port for self-test and hardware emulation.
There is no separate TRST input pin. An instruction reg-
ister, a boundary-scan register, a bypass register, and
a device identification register have been implemented.
The device identification register coding for the
DSP1627 is shown in Table 37. The instruction register
(IR) is 4 bits long. The instruction for accessing the de-
vice ID is 0xE (1110). The behavior of the instruction
register is summarized in Table 10. Cell 0 is the LSB
(closest to TDO).
The first line shows the cells in the IR that capture from
a parallel input in the capture-IR controller state. The
second line shows the cells that always load a logic 1 in
the capture-IR controller state. The third line shows the
cells that always load a logic 0 in the capture-IR control-
ler state. Cell 3 (MSB of IR) is tied to status signal PINT,
and cell 2 is tied to status signal JINT. The state of these
signals can therefore be captured during capture-IR and
shifted out during SHIFT-IR controller states.
Boundary-Scan Register
All of the chip's inputs and outputs are incorporated in a
JTAG scan path shown in Table 11. The types of
boundary-scan cells are as follows:
I
I = input cell
I
O = 3-state output cell
I
B = bidirectional (I/O) cell
I
OE = 3-state control cell
I
DC = bidirectional control cell
Table 10. JTAG Instruction Register
IR Cell #:
Parallel Input
Always Logic 1
Always Logic 0
3
Y
N
N
2
Y
N
N
1
N
N
Y
0
N
Y
N
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