Data Sheet
March 2000
DSP1627 Digital Signal Processor
74
Lucent Technologies Inc.
9 Electrical Characteristics and Requirements
(continued)
*
t
L
= PLL lock time (see Table 64).
T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).
The power dissipation listed is for internal power dissipation only. Total power dissipation can be calculated on the basis
of the application by adding C x V
DD
/2
x f for each output, where C is the additional load capacitance and f is the output
frequency.
Table 65. Power Dissipation and Wake-Up Latency
(continued)
Operating Mode
(Unused inputs at VDD or VSS)
Typical Power Dissipation (mW)
I/O Units ON
powerc[7:4] = 0x0
5 V
3 V
Wake-Up Latency
I/O Units OFF
powerc[7:4] = 0xf
5 V
(PLL Not Used
During Wake State)
5 V
(PLL Used
During Wake State)
5 V
3 V
3 V
3 V
Sleep with Slow Internal Clock
Crystal/Small Signal Enabled
powerc[15:14] = 01,
alf[15] = 1, ioc = 0x0180
PLL Enabled During Sleep
CMOS
8.3
27.5
10.0
3.0
9.9
4.5
7.5
24.5
10.0
2.7
8.8
4.0
—
—
—
1.5
μ
s
1.5
μ
s
1.5
μ
s
5.0
μ
s
5.0
μ
s
5.0
μ
s
Crystal Oscillator
Small Signal
Sleep with Slow Internal Clock
Crystal/Small Signal Disabled
powerc[15:14] = 11,
alf[15] = 1, ioc = 0x0180
PLL Disabled During Sleep
Crystal Oscillator
0.67
0.67
0.24
0.24
0.56
0.56
0.16
0.16
20 ms
20
μ
s
20 μs + t
L
20 μs + t
L
Small Signal
Software Stop
powerc[15:12] = 0011
PLL Disabled During STOP
CMOS
0.19
0.067
0.19
0.067
3T*
3T* + t
L
Software Stop
powerc[15:12] = 1111
PLL Disabled During STOP
Crystal Oscillator
0.19
0.19
0.067
0.067
0.19
0.19
0.067
0.067
20 ms
20
μ
s
20 μs +t
L
20 μs + t
L
Small Signal
Hardware Stop (STOP = V
SS
)
powerc[15:12] = 0000
PLL Disabled During STOP
CMOS
0.19
20.0
3.0
0.067
6.0
1.1
0.19
20.0
3.0
0.067
6.0
1.1
3T*
3T*
3T*
—
—
—
Crystal Oscillator
Small Signal
Hardware Stop (STOP = V
SS
)
powerc[15:12] = 0000
PLL Enabled During STOP
CMOS
5.6
25.6
8.6
2.4
8.4
3.5
5.6
25.6
8.6
2.4
8.4
3.5
3T*
3T*
3T*
3T*
3T*
3T*
Crystal Oscillator
Small Signal