參數(shù)資料
型號： DSP1627
英文描述： TVS 400W 6.5V BIDIRECT SMA
中文描述： DSP1627數(shù)字信號處理器
文件頁數(shù)： 71/154頁
文件大?。?/td> 2365K
代理商： DSP1627
Data Sheet
March 2000
DSP1627 Digital Signal Processor
Lucent Technologies Inc.
71
9 Electrical Characteristics and Requirements
(continued)
Additional Electrical Requirements with Crystal Option:
See Section 13, Crystal Electrical Characteristics and
Requirements.
Table 63. PLL Electrical Specifications, VCO Frequency Ranges
Parameter
Symbol
f
VCO
f
VCO
f
VCO
—
Min
50
50
70
—
Max
160
200
180
200
Unit
MHz
MHz
MHz
ps-rms
VCO frequency range (V
DD
= 3 V
±
10%)
*
VCO frequency range (V
DD
= 3.0 V –
3.6 V)*
VCO frequency range (V
DD
= 5 V
±
5%)*
Input Jitter at CKI
*
The M and N counter values in the pllc register must be set so that the VCO will operate in the appropriate range (see Table 63). Choose the
lowest value of N and then the appropriate value of M for
f
INTERNAL CLOCK
=
f
CKI
x (M/(2N)) =
f
VCO
/2.
Table 64. PLL Electrical Specifications and pllc Register Settings
M
V
DD
pllc13 (ICP)
pllc12
(SEL5V)
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
pllc[11:8]
(LF[3:0])
1011
1010
1001
1000
0111
0110
0100
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
Typical Lock-in Time (
μ
s)
*
*
Lock-in time represents the time following assertion of the PLLEN bit of the pllc register during which the PLL output clock is unstable. The
DSP must operate from the 1X CKI input clock or from the slow ring oscillator while the PLL is locking. Completion of the lock-in interval is
indicated by assertion of the LOCK flag.
23—24
21—22
19—20
16—18
12—15
8—11
2—7
19—20
17—18
16
14—15
12—13
10—11
8—9
7
5—6
2—4
2.7 V – 3.6 V
2.7 V – 3.6 V
2.7 V – 3.6 V
2.7 V – 3.6 V
2.7 V – 3.6 V
2.7 V – 3.6 V
2.7 V – 3.6 V
5 V
±
5%
5 V
±
5%
5 V
±
5%
5 V
±
5%
5 V
±
5%
5 V
±
5%
5 V
±
5%
5 V
±
5%
5 V
±
5%
5 V
±
5%
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
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