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參數(shù)資料
| 型號(hào)： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 62/154頁 |
| 文件大?。?/td> | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
62
Lucent Technologies Inc.
6 Signal Descriptions
(continued)
CKI
Input Clock:
A mask-programmable option selects one
of three possible input buffers for the CKI pin (see Sec-
tion 7, Mask-Programmable Options, and Table 1, Pin
Descriptions). The internal CKI from the output of the
selected input buffer can then drive the internal proces-
sor clock directly (1X) or drive the on-chip PLL (see Sec-
tion 4.13). The PLL allows the CKI input clock to be at a
lower frequency than the internal processor clock.
CKI2
Input Clock 2:
Used with mask-programmable input
clock options which require an external crystal or small
signal differential across CKI and CKI2 (see Table 1,
Pin Descriptions). When the CMOS option is selected,
this pin should be tied to V
SSA
.
STOP
Stop Input Clock:
Negative assertion. A high-to-low
transition synchronously stops all of the internal proces-
sor clocks leaving the processor in a defined state. Re-
turning the pin high will synchronously restart the
processor clocks to continue program execution from
where it left off without any loss of state. This hardware
feature has the same effect as setting the NOCK bit in
the powerc register (see Table 39).
CKO
Clock Out:
Buffered output clock with options program-
mable via the ioc register (see Table 38). The selectable
CKO options (see Tables 38 and 29) are as follows:
I
A free-running output clock at the frequency of the in-
ternal processor clock; runs at the internal ring oscilla-
tor frequency when SLOWCKI is enabled.
I
A wait-stated clock based on the internal instruction cy-
cle; runs at the internal ring oscillator frequency when
SLOWCKI is enabled.
I
A sequenced, wait-stated clock based on the EMI se-
quencer cycle; runs at the internal ring oscillator fre-
quency when SLOWCKI is enabled.
I
A free-running output clock that runs at the CKI rate, in-
dependent of the
powerc
register setting. This option
is only available with the crystal and small-signal clock
options. When the PLL is selected, the CKO frequency
equals the input CKI frequency regardless of how the
PLL is programmed.
I
A logic 0.
I
A logic 1.
INT[1:0]
Processor Interrupts 0 and 1:
Positive assertion.
Hardware interrupt inputs to the DSP1627. Each is en-
abled via the inc register. When enabled and asserted,
each cause the processor to vector to the memory loca-
tion described in Table 4. INT1 is used in conjunction
with EXM to select the desired reset initialization of the
mwait register (see Table 36). When both INT0 and
RSTB are asserted, all output and bidirectional pins (ex-
cept TDO, which 3-states by JTAG control) are put in a
3-state condition.
VEC[3:0]
Interrupt Output Vector:
These four pins indicate
which interrupt is currently being serviced by the device.
Table 4 shows the code associated with each interrupt
condition. VEC[3:0] are multiplexed with IOBIT[4:7].
IACK
Interrupt Acknowledge:
Positive assertion. IACK
signals when an interrupt is being serviced by the
DSP1627. IACK remains asserted while in an interrupt
service routine, and is cleared when the ireturn instruc-
tion is executed.
TRAP
Trap Signal:
Positive assertion. When asserted, the
processor is put into the trap condition, which normally
causes a branch to the location 0x0046. The hardware
development system (HDS) can configure the trap pin
to cause an HDS trap, which causes a branch to loca-
tion 0x0003. Although normally an input, the pin can be
configured as an output by the HDS. As an output, the
pin can be used to signal an HDS breakpoint in a multi-
ple processor environment.
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