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參數(shù)資料
| 型號(hào)： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 20/154頁(yè) |
| 文件大?。?/td> | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
20
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
The serial data may be internally looped back by setting
the SIO loopback control bit, SIOLBC, of the ioc regis-
ter. SIOLBC affects both the SIO and SIO2. The data
output signals are wrapped around internally from the
output to the input (DO1 to DI1 and DO2 to DI2). To ex-
ercise loopback, the SIO clocks (ICK1, ICK2, OCK1,
and OCK2) should either all be in the active mode,
16-bit condition, or each pair should be driven from one
external source in passive mode. Similarly, pins ILD1
(ILD2) and OLD1 (OLD2) must both be in active mode
or tied together and driven from one external frame
clock in passive mode. During loopback, DO1, DO2,
DI1, DI2, ICK1, ICK2, OCK1, OCK2, ILD1, ILD2, OLD1,
OLD2, SADD1, SADD2, SYNC1, SYNC2, DOEN1, and
DOEN2 are 3-stated.
Setting DODLY = 1 (sioc and sioc2) delays DO by one
phase of OCK so that DO changes on the falling edge
of OCK instead of the rising edge (DODLY = 0). This re-
duces the time available for DO to drive DI and to be val-
id for the rising edge of ICK, but increases the hold time
on DO by half a cycle on OCK.
Programmable Modes
Programmable modes of operation for the SIO and
SIO2 are controlled by the serial I/O control registers
(sioc and sioc2). These registers, shown in Table 22,
are used to set the ports into various configurations.
Both input and output operations can be independently
configured as either active or passive. When active, the
DSP1627 generates load and clock signals. When pas-
sive, load and clock signal pins are inputs.
Since input and output can be independently config-
ured, each SIO has four different modes of operation.
Each of the sioc registers is also used to select the fre-
quency of active clocks for that SIO. Finally, these reg-
isters are used to configure the serial I/O data formats.
The data can be 8 or 16 bits long, and can also be input/
output MSB first or LSB first. Input and output data for-
mats can be independently configured.
Multiprocessor Mode
The multiprocessor mode allows up to eight processors
(DSP1629, DSP1628, DSP1627, DSP1620, DSP1618,
DSP1617, DSP1616, DSP1611) to be connected to-
gether to provide data transmission among any of the
DSPs in the system. Either SIO port (SIO or SIO2) may
be independently used for the multiprocessor mode.
The multiprocessor interface is a four-wire interface,
consisting of a data channel, an address/protocol
channel, a transmit/receive clock, and a sync signal
(see Figure 5). The DI1 and DO1 pins of all the DSPs
are connected to transmit and receive the data channel.
The SADD1 pins of all the DSPs are connected to trans-
mit and receive the address/protocol channel. ICK1 and
OCK1 should be tied together and driven from one
source. The SYNC1 pins of all the DSPs are connected.
In the configuration shown in Figure 5, the master DSP
(DSP0) generates active SYNC1 and OCK1 signals
while the slave DSPs use the SYNC1 and OCK1 signals
in passive mode to synchronize operations. In addition,
all DSPs must have their ILD1 and OLD1 signals in ac-
tive mode.
While ILD1 and OLD1 are not required externally for
multiprocessor operation, they are used internally in the
DSP's SIO. Setting the LD field of the master's sioc reg-
ister to a logic level 1 will ensure that the active genera-
tion of SYNC1, ILD1, and OLD1 is derived from OCK1
(see Table 22). With this configuration, all DSPs should
use ICK1 (tied to OCK1) in passive mode to avoid con-
flicts on the clock (CK) line (see the DSP1611/17/18/27
Digital Signal Processor Information Manual for more
information).
Four registers (per SIO) configure the multiprocessor
mode: the time-division multiplexed slot register (tdms
or tdms2), the serial receive and transmit address reg-
ister (srta or srta2), the serial data transmit register (sdx
or sdx2), and the multiprocessor serial address/protocol
register (saddx or saddx2).
Multiprocessor mode requires no external logic and
uses a TDM interface with eight 16-bit time slots per
frame. The transmission in any time slot consists of
16 bits of serial data in the data channel and 16 bits of
address and protocol information in the address/proto-
col channel. The address information consists of the
transmit address field of the srta register of the transmit-
ting device. The address information is transmitted con-
currently with the transmission of the first 8 bits of data.
The protocol information consists of the transmit proto-
col field written to the saddx register and is transmitted
concurrently with the last 8 bits of data (see Table 25,
Multiprocessor Protocol Register). Data is received or
recognized by other DSP(s) whose receive address
matches the address in the address/protocol channel.
Each SIO port has a user-programmable receive ad-
dress and transmit address associated with it. The
transmit and receive addresses are programmed in the
srta register.
In multiprocessor mode, each device can send data in
a unique time slot designated by the tdms register trans-
mit slot field (bits 7—0). The tdms register has a fully de-
coded transmit slot field in order to allow one DSP1627
device to transmit in more than one time slot. This pro-
cedure is useful for multiprocessor systems with less
than eight DSP1627 devices when a higher bandwidth
is necessary between certain devices in that system.
The DSP operating during time slot 0 also drives
SYNC1.
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| DSP25 | Phase-leg Rectifier Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DSP1627F32K10IR | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K10IT | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11I | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:16-Bit Digital Signal Processor |
| DSP1627F32K11IR | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11IT | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
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