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參數(shù)資料
| 型號(hào)： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 64/154頁(yè) |
| 文件大?。?/td> | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
64
Lucent Technologies Inc.
6 Signal Descriptions
(continued)
6.3 Serial Interface #1
The serial interface pins implement a full-featured syn-
chronous/asynchronous serial I/O channel. In addition,
several pins offer a glueless TDM interface for multipro-
cessing communication applications (see Figure 5, Mul-
tiprocessor Communications and Connections).
DI1
Data Input:
Serial data is latched on the rising edge of
ICK1, either LSB or MSB first, according to the sioc reg-
ister MSB field (see Table 22).
ICK1
Input Clock:
The clock for serial input data. In active
mode, ICK1 is an output; in passive mode, ICK1 is an
input, according to the sioc register ICK field (see
Table 22). Input has typically 0.7 V hysteresis.
ILD1
Input Load:
The clock for loading the input buffer,
sdx[in], from the input shift register isr. A falling edge of
ILD1 indicates the beginning of a serial input word. In
active mode, ILD1 is an output; in passive mode, ILD1
is an input, according to the sioc register ILD field (see
Table 22). Input has typically 0.7 V hysteresis.
IBF1
Input Buffer Full:
Positive assertion. IBF1 is asserted
when the input buffer, sdx[in], is filled. IBF1 is negated
by a read of the buffer, as in a0 = sdx. IBF1 is also ne-
gated by asserting RSTB.
DO1
Data Output:
The serial data output from the output
shift register (osr), either LSB or MSB first (according to
the sioc register MSB field). DO1 changes on the rising
edges of OCK1. DO1 is 3-stated when DOEN1 is high.
DOEN1
Data Output Enable:
Negative assertion. An input
when not in the multiprocessor mode. DO1 and SADD1
are enabled only if DOEN1 is low. DOEN1 is bidirection-
al when in the multiprocessor mode (tdms register
MODE field set). In the multiprocessor mode, DOEN1
indicates a valid time slot for a serial output.
OCK1
Output Clock:
The clock for serial output data. In active
mode, OCK1 is an output; in passive mode, OCK1 is an
input, according to the sioc register OCK field (see Ta-
ble 22). Input has typically 0.7 V hysteresis.
OLD1
Output Load:
The clock for loading the output shift reg-
ister, osr, from the output buffer sdx[out]. A falling edge
of OLD1 indicates the beginning of a serial output word.
In active mode, OLD1 is an output; in passive, OLD1 is
an input, according to the sioc register OLD field (see
Table 22). Input has typically 0.7 V hysteresis.
OBE1
Output Buffer Empty:
Positive assertion. OBE1 is as-
serted when the output buffer, sdx[out], is emptied
(moved to the output shift register for transmission).
It is cleared with a write to the buffer, as in sdx = a0.
OBE1 is also set by asserting RSTB.
SADD1
Serial Address:
Negative assertion. A 16-bit serial bit
stream typically used for addressing during multiproces-
sor communication between multiple DSP16xx devices.
In multiprocessor mode, SADD1 is an output when the
tdms time slot dictates a serial transmission; otherwise,
it is an input. Both the source and destination DSP can
be identified in the transmission. SADD1 is always an
output when not in multiprocessor mode and can be
used as a second 16-bit serial output. See the
DSP1611/17/18/27 Digital Signal Processor Informa-
tion Manual or additional information. SADD1 is 3-stat-
ed when DOEN1 is high. When used on a bus, SADD1
should be pulled high through a 5 k
resistor.
SYNC1
Multiprocessor Synchronization:
Typically used in
the multiprocessor mode, a falling edge of SYNC1 indi-
cates the first word (time slot 0) of a TDM I/O stream
and causes the resynchronization of the active ILD1
and OLD1 generators. SYNC1 is an output when the
tdms register SYNC field is set (i.e., selects the master
DSP and uses time slot 0 for transmit). As an input,
SYNC1 must be tied low unless part of a TDM interface.
When used as an output, SYNC1 = [ILD1/OLD1]/8 or
16, depending on the setting of the SYNCSP field of the
tdms register. When configured as described above,
SYNC1 can be used to generate a slow clock for SIO
operations. Input has typically 0.7 V hysteresis.
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