參數(shù)資料
型號： EVAL-ADAU1781Z
廠商： Analog Devices Inc
文件頁數(shù)： 18/92頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1781
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻編解碼器
嵌入式： 是，DSP
已用 IC / 零件： ADAU1781
主要屬性： 立體聲，24 位，8 ~ 96 kHz 采樣率，GUI 工具
次要屬性： *
已供物品： *
ADAU1781
Rev. B| Page 25 of 92
STARTUP, INITIALIZATION, AND POWER
This section details the procedure for setting up the ADAU1781
properly. Figure 26 provides an overview of how to initialize the IC.
START
CONFIGURE CLOCK GENERATION
REGISTER 16384 (0x4000)
AND REGISTER 16386 (0x4002)
SUPPLY POWER TO AVDD1/AVDD2
PINS SIMULTANEOUSLY
DOWNLOAD PROGRAM RAM,
PARAMETER RAM, AND
REGISTER CONTENTS
INITIALIZATION
COMPLETE
WAIT 14ms FOR POWER-ON RESET
AND INITIALIZATION ROM BOOT
SUPPLY POWER TO IOVDD
ENABLE DIGITAL POWER TO
FUNCTIONAL SUBSYSTEMS
REGISTER 16512 (0x4080)
AND REGISTER 16513 (0x4081)
WAIT FOR PLL LOCK
(2.4ms TO 3.5ms)
ARE AVDD1 AND AVDD2
SUPPLIED SEPARATELY?
CAN AVDD1 AND AVDD2
BE SIMULTANEOUSLY
SUPPLIED?
SUPPLY POWER
TO AVDD2
SUPPLY POWER
TO AVDD1
NO
YES
NO
08314-
025
Figure 26. Initialization Sequence
POWER-UP SEQUENCE
If AVDD1 and AVDD2 are from the same supply, they can
power up simultaneously. If AVDD1 and AVDD2 are from
separate supplies, then AVDD1 should be powered up first.
IOVDD should be applied simultaneously with AVDD1, if
possible.
The ADAU1781 uses a power-on reset (POR) circuit to reset the
registers upon power-up. The POR monitors the DVDDOUT
pin and generates a reset signal whenever power is applied to
the chip. During the reset, the ADAU1781 is set to the default
values documented in the register map (see the Control Register
Map section).
The POR is also used to prevent clicks and pops on the speaker
driver output. The power-up sequencing and timing involved is
described in Figure 27 in this section, and in Figure 35 and
A self-boot ROM initializes the memories after the POR has
completed. When the self-boot sequence is complete, the control
registers are accessible via the I2C/SPI control port and should
then be configured as required for the application. Typically,
with a 10 μF capacitor on AVDD1, the power supply ramp-up,
POR, and self-boot combined take approximately 14 ms.
AVDD1
AVDD2
DVDDOUT
POWER-UP
(INTERNAL
SIGNAL)
INTERNAL MCLK
(NOT TO SCALE)
IOVDD
INPUT/OUTPUT
PINS
ACTIVE
1.35V
1.5V
0.95V
MAIN SUPPLY ENABLED
POR
ACTIVE
1.5V
MAIN SUPPLY DISABLED
14ms
HIGH-Z
POR COMPLETE/SELF-BOOT INITIATES
SELF-BOOT COMPLETE/MEMORY
IS ACCESSIBLE
POR ACTIVATES
08314-
026
Figure 27. Power-Up and Power-Down Sequence Timing Diagram
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