Table 14. Bas" />
參數(shù)資料
型號(hào)： EVAL-ADAU1781Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/92頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR ADAU1781
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻編解碼器
嵌入式： 是，DSP
已用 IC / 零件： ADAU1781
主要屬性： 立體聲，24 位，8 ~ 96 kHz 采樣率，GUI 工具
次要屬性： *
已供物品： *
ADAU1781
Rev. B | Page 28 of 92
Table 14 and Table 15 list the sampling rate divisions for
common base sampling rates.
Table 14. Base Sampling Rate Divisions for fS = 48 kHz
Base Sampling
Frequency
Sampling Rate Scaling
Sampling Rate
f
S = 48 kHz
f
S/1
48 kHz
f
S/6
8 kHz
f
S/4
12 kHz
f
S/3
16 kHz
f
S/2
24 kHz
f
S/1.5
32 kHz
f
S/0.5
96 kHz
Table 15. Base Sampling Rate Divisions for fS = 44.1 kHz
Base Sampling
Frequency
Sampling Rate Scaling
Sampling Rate
f
S = 44.1 kHz
f
S/1
44.1 kHz
f
S/6
7.35 kHz
f
S/4
11.025 kHz
f
S/3
14.7 kHz
f
S/2
22.05 kHz
f
S/1.5
29.4 kHz
f
S/0.5
88.2 kHz
PLL
The PLL uses the MCLK as a reference to generate the core
clock. PLL settings are set in Register 16386 (0x4002), PLL
control. Depending on the MCLK frequency, the PLL must be
set for either integer or fractional mode. The PLL can accept
input frequencies in the range of 11 MHz to 20 MHz.
All six bytes in the PLL control register must be written with a
single continuous write to the control port.
MCKI
÷ X
× (R + N/M)
TO PLL
CLOCK DIVIDER
08314-
028
Figure 29. PLL Block Diagram
Integer Mode
Integer mode is used when the MCLK is an integer (R) multiple
of the PLL output (1024 × fS).
For example, if MCLK = 12.288 MHz and fS = 48 kHz, then
PLL Required Output = 1024 × 48 kHz = 49.152 MHz
R = 49.152 MHz/12.288 MHz = 4
In integer mode, the values set for N and M are ignored.
Fractional Mode
Fractional mode is used when the MCLK is a fractional
(R + (N/M)) multiple of the PLL output.
For example, if MCLK = 12 MHz and fS = 48 kHz, then
PLL Required Output = 1024 × 48 kHz = 49.152 MHz
R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)
Common fractional PLL parameter settings for 44.1 kHz and
48 kHz sampling rates can be found in Table 16 and Table 17.
Table 16. Fractional PLL Parameter Settings for fS = 44.1 kHz1
MCLK
Input
(MHz)
Input
Divider
(X)
Integer
(R)
Denominator
(M)
Numerator
(N)
12
1
3
625
477
13
1
3
8125
3849
14.4
2
6
125
34
19.2
2
4
125
88
19.68
2
4
1025
604
19.8
2
4
1375
772
1 Desired core clock = 11.2896 MHz, PLL output = 45.1584 MHz.
Table 17. Fractional PLL Parameter Settings for fS = 48 kHz1
MCLK
Input
(MHz)
Input
Divider
(X)
Integer
(R)
Denominator
(M)
Numerator
(N)
12
1
4
125
12
13
1
3
1625
1269
14.4
2
6
75
62
19.2
2
5
25
3
19.68
2
4
205
204
19.8
2
4
825
796
1 Desired core clock = 12.288 MHz, PLL output = 49.152 MHz.
The PLL outputs a clock in the range of 41 MHz to 54 MHz,
which should be taken into account when calculating PLL
values and MCLK frequencies.
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