Master clock = 12.288 MHz, PLL is active in integer mode at a 25" />
參數(shù)資料
型號： EVAL-ADAU1781Z
廠商： Analog Devices Inc
文件頁數(shù)： 89/92頁
文件大小： 0K
描述： BOARD EVAL FOR ADAU1781
標準包裝： 1
系列： SigmaDSP®
主要目的： 音頻編解碼器
嵌入式： 是，DSP
已用 IC / 零件： ADAU1781
主要屬性： 立體聲，24 位，8 ~ 96 kHz 采樣率，GUI 工具
次要屬性： *
已供物品： *
ADAU1781
Rev. B| Page 9 of 92
TYPICAL POWER MANAGEMENT MEASUREMENTS
Master clock = 12.288 MHz, PLL is active in integer mode at a 256 × fS input rate for fS = 48 kHz, analog and digital input tones are
1 dBFS with a frequency of 1 kHz. Analog input and output are simultaneously active. Pseudo differential stereo input is routed to
ADCs, and DACs are routed to stereo line output with a 16 kΩ load. ADC input at 1 dBFS, DAC input at 0 dBFS. The speaker output is
disabled. The serial port is configured in slave mode. The beep path is disabled. SigmaDSP processing is enabled. Current measurements
are given in units of mA rms.
Table 4. Mixer Boost and Power Management Conditions
Operating Voltage
Power Management Mode1
Mixer Boost Mode2
Typical AVDD Current
Consumption (mA)
Typical ADC
THD + N (dB)
Typical Line Output
THD + N (dB)
AVDD = IOVDD = 3.3 V
Normal (default)
Normal operation
16.84
88.5
93.0
Boost Level 1
16.88
88.5
93.0
Boost Level 2
16.92
88.5
93.0
Boost Level 3
17.00
88.5
93.0
Extreme power saving
Normal operation
15.66
88.0
87.5
Boost Level 1
15.68
88.0
87.5
Boost Level 2
15.70
88.0
87.5
Boost Level 3
15.75
88.0
87.5
Enhanced performance
Normal operation
17.43
88.5
94.5
Boost Level 1
17.50
88.5
94.5
Boost Level 2
17.53
88.5
94.5
Boost Level 3
17.63
88.5
94.5
Power saving
Normal operation
16.25
89.0
90.5
Boost Level 1
16.28
89.0
90.5
Boost Level 2
16.31
89.0
90.5
Boost Level 3
16.38
89.0
90.5
AVDD = IOVDD = 1.8 V
Normal (default)
Normal operation
15.15
88.5
89.5
Boost Level 1
15.19
88.5
89.5
Boost Level 2
15.23
88.5
89.5
Boost Level 3
15.30
88.5
89.5
Extreme power saving
Normal operation
14.03
86.5
85.5
Boost Level 1
14.05
86.5
85.5
Boost Level 2
14.07
86.5
85.5
Boost Level 3
14.12
86.5
85.5
Enhanced performance
Normal operation
15.71
88.5
90.5
Boost Level 1
15.76
88.5
90.5
Boost Level 2
15.81
88.5
90.5
Boost Level 3
15.89
88.5
90.5
Power saving
Normal operation
14.59
88.0
Boost Level 1
14.62
88.0
Boost Level 2
14.65
88.0
Boost Level 3
14.71
88.0
1 Set by Register 0x4009, Bits[4:1], and Register 0x4029, Bits[5:2].
2 Set by Register 0x4009, Bits[6:5].
DIGITAL FILTERS
Table 5.
Parameter
Mode
Factor
Min
Typ
Max
Unit
ADC DECIMATION FILTER
All modes, typ value is for 48 kHz
Pass Band
0.4375 × f
S
21
kHz
Pass-Band Ripple
±0.015
dB
Transition Band
0.5 × f
S
24
kHz
Stop Band
0.5625 × f
S
27
kHz
Stop-Band Attenuation
70
dB
Group Delay
22.9844/f
S
479
s
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