參數(shù)資料
型號(hào): EVAL-ADAU1781Z
廠商: Analog Devices Inc
文件頁(yè)數(shù): 80/92頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADAU1781
標(biāo)準(zhǔn)包裝: 1
系列: SigmaDSP®
主要目的: 音頻編解碼器
嵌入式: 是,DSP
已用 IC / 零件: ADAU1781
主要屬性: 立體聲,24 位,8 ~ 96 kHz 采樣率,GUI 工具
次要屬性: *
已供物品: *
ADAU1781
Rev. B| Page 81 of 92
Register 16434 (0x4032), Dejitter Control
Bits[7:0], Dejitter Window Size
The dejitter control register not only allows the size of the
dejitter window to be set, but also allows all dejitter circuits in
the device to be activated or bypassed. Dejitter circuits protect
against duplicate samples or skipped samples due to jitter from
the serial ports in slave mode. Disabling and reenabling certain
subsystems in the device—that is, the ADCs, serial ports, sound
engine/DSP core, and DACs—during operation can cause the
associated dejitter circuits to fail. As a result, audio data fails to
be output to the next subsystem in the device.
When the serial ports are in master mode, the dejitter circuit
can be bypassed by setting the dejitter window to 0. When the
serial ports are in slave mode, the dejitter circuit can be reinitialized
prior to outputting audio from the device, guaranteeing that audio
is output to the next subsystem in the device. Any time audio
needs to pass through the ADCs, serial port, sound engine/DSP
core, or DACs, the dejitter circuit can be bypassed and reset by
setting the dejitter window size to 0. Then, the dejitter circuit can
be immediately reactivated, without a wait period, by setting the
dejitter window size to the default value of 5.
Table 70. Dejitter Control Register
Bits
Description
Default
[7:0]
Dejitter window size
00000101
00000000: 0 core clock cycles
00000101: 5 core clock cycles
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