參數(shù)資料
型號(hào)： EVAL-ADAU1781Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/92頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1781
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻編解碼器
嵌入式： 是，DSP
已用 IC / 零件： ADAU1781
主要屬性： 立體聲，24 位，8 ~ 96 kHz 采樣率，GUI 工具
次要屬性： *
已供物品： *
ADAU1781
Rev. B | Page 38 of 92
SERIAL DATA INPUT/OUTPUT PORTS
The flexible serial data input and output ports of the ADAU1781
can be set to accept or transmit data in 2-channel format or in a
4-channel or 8-channel TDM stream to interface to external ADCs
or DACs. Data is processed by default in twos complement, MSB
first format, unless otherwise configured in the control registers.
By default, the left channel data field precedes the right channel
data field in 2-channel streams. In TDM 4 mode, Slot 0 and Slot 1
are in the first half of the audio frame, and Slot 2 and Slot 3 are
in the second half of the audio frame. In TDM 8 mode, Slot 0 to
Slot 3 are in the first half of the audio frame, and Slot 4 to Slot 7
are in the second half of the frame. The serial modes and the
position of the data in the frame are set in Register 16405 (0x4015),
Serial Port Control 0; Register 16406 (0x4016), Serial Port Control 1;
Register 16407 (0x4017), Converter Control 0; and Register 16408
(0x4018), Converter Control 1.
The serial data clocks must be synchronous with the ADAU1781
master clock input. The LRCLK and BCLK pins are used to clock
both the serial input and output ports. The ADAU1781 can be
set as the master or the slave in a system. Because there is only
one set of serial data clocks, the input and output ports must
always be both master or both slave.
Register 16405 (0x4015), Serial Port Control 0, and Register
16406 (0x4016), Serial Port Control 1, allow control of clock
polarity and data input modes. The valid data formats are I2S,
left-justified, right-justified (24-/20-/18-/16-bit), and TDM. In
all modes except for the right-justified modes, the serial port
inputs an arbitrary number of audio data bits, up to a limit of 24.
Extra bits do not cause an error, but they are truncated internally.
The serial port can operate with an arbitrary number of BCLK
transitions in each LRCLK frame.
TDM MODES
The LRCLK in TDM mode can be input to the ADAU1781
either as a 50% duty cycle clock or as a bit-wide pulse.
When the LRCLK is set as a pulse, a 47 pF capacitor should be
connected between the LRCLK pin and ground, as shown in
Figure 45. This is necessary in both master and slave modes to
properly align the LRCLK signal to the serial data stream.
ADAU1781
LRCLK
BCLK
47pF
08314-
044
Figure 45. TDM Pulse Mode LRCLK Capacitor Alignment
The ADAU1781 TDM implementation is a TDM audio stream.
Unlike a true TDM bus, its output does not become high imped-
ance during periods when it is not transmitting data.
In TDM 8 mode, the ADAU1781 can be a master for fS up to
48 kHz. Table 25 lists the modes in which the serial output port
can function.
Table 25. Serial Output Port Master/Slave Mode Capabilities
f
S
2-Channel Modes (I2S, Left-
Justified, Right-Justified)
8-Channel TDM
48 kHz
Master and slave
96 kHz
Master and slave
Slave
Table 26 describes the proper configurations for standard audio
data formats. Right-justified modes must be configured manually
using Register 16406 (0x4016), Serial Port Control 1, Bits[7:5],
number of bit clock cycles per frame, and Bits[1:0], data delay
from LRCLK edge.
Table 26. Data Format Configurations
Format
LRCLK Polarity
LRCLK Mode
BCLK Polarity
BCLK Cycles/
Audio Frame
Data Delay from
LRCLK Edge
Frame begins on falling edge
50% duty cycle
Data changes
on falling edge
64
Delayed from LRCLK edge
by 1 BCLK
Left-Justified
Frame begins on rising edge
50% duty cycle
Data changes
on falling edge
64
Aligned with LRCLK edge
Right-Justified
Frame begins on rising edge
50% duty cycle
Data changes
on falling edge
64
Delayed from LRCLK edge
by 8, 12, or 16 BCLKs to
align LSB with right edge
of frame.
TDM with Clock
Frame begins on falling edge
50% duty cycle
Data changes
on falling edge
64 to 256
Delayed from start of word
clock by 1 BCLK
TDM with Pulse
Frame begins on rising edge
Pulse
Data changes
on falling edge
64 to 256
Delayed from start of word
clock by 1 BCLK
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