參數(shù)資料
型號： EVAL-ADAU1781Z
廠商： Analog Devices Inc
文件頁數(shù)： 44/92頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1781
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻編解碼器
嵌入式： 是，DSP
已用 IC / 零件： ADAU1781
主要屬性： 立體聲，24 位，8 ~ 96 kHz 采樣率，GUI 工具
次要屬性： *
已供物品： *
ADAU1781
Rev. B| Page 49 of 92
CLOCK MANAGEMENT, INTERNAL REGULATOR,
AND PLL CONTROL
Register 16384 (0x4000), Clock Control
The clock control register sets the clocking scheme for the
ADAU1781. The system clock can be generated from either the
PLL or directly from the MCKI (master clock input) pin. Addi-
tionally, the MCKO (master clock output) pin can be configured.
Bits[6:5], MCKO Frequency
These bits set the frequency to be output on MCKO as a multiple
of the base sampling frequency (32×, 64×, 128×, or 256×). The
MCKO pin can be used to provide digital microphones with a clock.
Bit 4, MCKO Enable
This bit enables or disables the MCKO pin.
Bit 3, Clock Source Select
The clock source select bit either routes the MCLK input through
the PLL or bypasses the PLL. When using the PLL, the output of
the PLL is always 1024 × fS, and Bits[2:1] should be set to 11.
PLL parameters can be set in the PLL control register. Inputs
directly from MCKI require an exact clock rate as described in
Bits[2:1], Input Master Clock Frequency
The maximum clock speed allowed is 1024 × 48 kHz. These bits set
the expected input master clock frequency for proper clock divider
values in order to output a constant system clock of 256 × fS. When
using the PLL, these bits must always be set to 1024 × fS. When
bypassing the PLL, the external clock frequency on the MCKI pin
must be 256 × fS, 512 × fS, 768 × fS, or 1024 × fS. Table 35 and
Table 36 show the relationship between the system clock and the
internal master clock for base sampling frequencies of 44.1 kHz
and 48 kHz.
Bit 0, Core Clock Enable
This bit enables the internal master clock to start the IC.
Table 34. Clock Control Register
Bits
Description
Default
7
Reserved
[6:5]
MCKO frequency
00
00: 32 × fS
01: 64 × fS
10: 128 × fS
11: 256 × fS
4
MCKO enable
0
0: disabled
1: enabled
3
Clock source select
0
0: direct from MCKI pin
1: PLL clock
[2:1]
Input master clock frequency
00
00: 256 × fS
01: 512 × fS
10: 768 × fS
11: 1024 × fS
0
Core clock enable
0
0: core clock disabled
1: core clock enabled
Table 35. Core Clock Output for fS = 44.1 kHz
MCLK Input Setting
MCLK Input Value
MCLK Input Divider
Core Clock
256 × fS
11.2896 MHz
1
11.2896 MHz
512 × fS
22.5792 MHz
2
11.2896 MHz
768 × fS
33.8688 MHz
3
11.2896 MHz
1024 × fS
45.1584 MHz
4
11.2896 MHz
Table 36. Core Clock Output for fS = 48 kHz
MCLK Input Setting
MCLK Input Value
MCLK Input Divider
Core Clock
256 × fS
12.288 MHz
1
12.288 MHz
512 × fS
24.576 MHz
2
12.288 MHz
768 × fS
36.864 MHz
3
12.288 MHz
1024 × fS
49.152 MHz
4
12.288 MHz
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