參數(shù)資料
型號(hào): EVAL-ADAU1781Z
廠商: Analog Devices Inc
文件頁(yè)數(shù): 47/92頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADAU1781
標(biāo)準(zhǔn)包裝: 1
系列: SigmaDSP®
主要目的: 音頻編解碼器
嵌入式: 是,DSP
已用 IC / 零件: ADAU1781
主要屬性: 立體聲,24 位,8 ~ 96 kHz 采樣率,GUI 工具
次要屬性: *
已供物品: *
ADAU1781
Rev. B| Page 51 of 92
Table 38. PLL Control Register
Bits
Description
Default
[47:40]
Denominator MSB
00000111
00000000 and 00000000: M[15:8] and M[7:0] = 0
00000000 and 11111101: M[15:8] and M[7:0] = 125
11111111 and 11111111: M[15:8] and M[7:0] = 65,535
[39:32]
Denominator LSB
01010011
00000000 and 00000000: M[15:8] and M[7:0] = 0
00000000 and 11111101: M[15:8] and M[7:0] = 125
11111111 and 11111111: M[15:8] and M[7:0] = 65,535
[31:24]
Numerator MSB
00000010
00000000 and 00000000: N[15:8] and N[7:0] = 0
00000000 and 00001100: N[15:8] and N[7:0] = 12
11111111 and 11111111: N[15:8] and N[7:0] = 65,535
[23:16]
Numerator LSB
10000111
00000000 and 00000000: N[15:8] and N[7:0] = 0
00000000 and 00001100: N[15:8] and N[7:0] = 12
11111111 and 11111111: N[15:8] and N[7:0] = 65,535
15
Reserved
[14:11]
Integer
0011
0010: R = 2
0011: R = 3
0100: R = 4
0101: R = 5
0110: R = 6
0111: R = 7
1000: R = 8
[10:9]
Input divider
00
00: no division
01: divide by X = 2
10: divide by X = 3
11: divide by X = 4
8
PLL type
1
0: integer-N
1: fractional
[7:2]
Reserved
1
PLL lock (read only)
1
0: unlocked
1: locked (sticky bit)
0
PLL enable
1
0: disabled
1: enabled
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