參數(shù)資料
型號: EVAL-ADAU1781Z
廠商: Analog Devices Inc
文件頁數(shù): 72/92頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADAU1781
標(biāo)準(zhǔn)包裝: 1
系列: SigmaDSP®
主要目的: 音頻編解碼器
嵌入式: 是,DSP
已用 IC / 零件: ADAU1781
主要屬性: 立體聲,24 位,8 ~ 96 kHz 采樣率,GUI 工具
次要屬性: *
已供物品: *
ADAU1781
Rev. B | Page 74 of 92
Register 16427 (0x402B), Left DAC Attenuator
Bits[7:0], Left DAC Digital Attenuator
These bits control a 256-step, logarithmically spaced volume
control from 0 dB to 95.625 dB, in increments of 0.375 dB.
When a new value is entered into this register, the volume control
slews gradually to the new value, avoiding pops and clicks in the
process. The slew ramp is logarithmic, incrementing 0.375 dB
per audio frame.
Register 16428 (0x402C), Right DAC Attenuator
Bits[7:0], Right DAC Digital Attenuator
These bits control a 256-step, logarithmically spaced volume
control from 0 dB to 95.625 dB, in increments of 0.375 dB.
When a new value is entered into this register, the volume control
slews gradually to the new value, avoiding pops and clicks in the
process. The slew ramp is logarithmic, incrementing 0.375 dB
per audio frame.
Table 63. Left DAC Attenuator Register
Bits
Description
Default
[7:0]
Left DAC digital attenuator, in increments of 0.375 dB with each step of slewing
00000000
00000000: 0 dB
00000001: 0.375 dB
00000010: 0.75 dB
11111110: 95. 25
11111111: 95.625 dB
Table 64. Right DAC Attenuator Register
Bits
Description
Default
[7:0]
Right DAC digital attenuator, in increments of 0.375 dB with each step of slewing
00000000
00000000: 0 dB
00000001: 0.375 dB
00000010: 0.75 dB
11111110: 95. 25
11111111: 95.625 dB
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