參數(shù)資料
型號: EVAL-ADAU1781Z
廠商: Analog Devices Inc
文件頁數(shù): 78/92頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADAU1781
標(biāo)準(zhǔn)包裝: 1
系列: SigmaDSP®
主要目的: 音頻編解碼器
嵌入式: 是,DSP
已用 IC / 零件: ADAU1781
主要屬性: 立體聲,24 位,8 ~ 96 kHz 采樣率,GUI 工具
次要屬性: *
已供物品: *
ADAU1781
Rev. B | Page 8 of 92
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Total Harmonic Distortion + Noise
8 , 1 nF load, AVDD = 1.8 V, P
O = 50 mW
60
dB
AVDD = 3.3 V, P
O = 175 mW
60
dB
Dynamic Range
60 dB input
With A-Weighted Filter (RMS)
AVDD = 1.8 V
97
dB
AVDD = 3.3 V
103
dB
No Filter (RMS)
AVDD = 1.8 V
94
dB
AVDD = 3.3 V
100
dB
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
AVDD = 1.8 V
98
dB
AVDD = 3.3 V
103
dB
No Filter (RMS)
AVDD = 1.8 V
96
dB
AVDD = 3.3 V
101
dB
Power Supply Rejection Ratio
CM capacitor = 10 μF
100 mV p-p at 217 Hz
57
dB
100 mV p-p at 1 kHz
60
dB
Differential Offset Error
2
mV
Mono Mixer Mute Attenuation,
Beep to Mixer Path Muted
Mute set by Register 0x401F, Bit 0
90
dB
REFERENCE (CM PIN)
Common-Mode Reference Output
AVDD/2
V
POWER SUPPLY SPECIFICATIONS
AVDD1 and AVDD2 must always be equal. Power supply measurements are taken with the SigmaDSP processing core enabled.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
AVDD1, AVDD2
1.81
3.3
3.65
V
IOVDD
1.63
3.3
3.65
V
Digital I/O Current (IOVDD = 3.3 V)
20 pF capacitive load on all digital pins
Slave Mode, Analog I/O,
12.288 MHz External MCLK Input
f
S = 48 kHz
0.20
mA
f
S = 96 kHz
0.35
mA
f
S = 8 kHz
0.04
mA
Master Mode, MCKO Disabled
f
S = 48 kHz
1.25
mA
f
S = 96 kHz
2.50
mA
f
S = 8 kHz
0.22
mA
Digital I/O Current (IOVDD = 1.8 V)
20 pF capacitive load on all digital pins
Slave Mode, Analog I/O,
12.288 MHz External MCLK Input
f
S = 48 kHz
0.10
mA
f
S = 96 kHz
0.18
mA
f
S = 8 kHz
0.02
mA
Master Mode, MCKO Disabled
f
S = 48 kHz
0.68
mA
f
S = 96 kHz
1.33
mA
f
S = 8 kHz
0.12
mA
Analog Current (AVDD)
1 The zero-cross detection of the beep path is not supported at AVDD1, AVDD2 < 2.2 V.
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