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參數(shù)資料
| 型號： | GS4576S09L-25 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA144 |
| 封裝： | UBGA-144 |
| 文件頁數(shù)： | 14/64頁 |
| 文件大小： | 2691K |
| 代理商： | GS4576S09L-25 |
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Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
21/64
2011, GSI Technology
Write
Write data transfers are launched with a Write command, as shown below. A valid address must be provided during the Write
command.
During Write data transfers, each beat of incoming data is registered on crossings of DK and DK until the burst transfer is
complete. Write Latency (WL) that is always one cycle longer than the programmed Read Latency (RL), so the first valid data
registered at the first True crossing of the DK clocks WL cycles after the Write command.
Since the input and output buses are separated, any Write burst may be followed by a subsequent Read command without
encountering external data bus contention. The Write-to-Read timing diagrams illustrate the timing requirements for a Write
followed by a Read. Setup and hold times for incoming D relative to the DK edges are specified as tDS and tDH. Input data may be
masked a High on an associated DM pin. The setup and hold times for the DM signal are tDS and tDH.
Write Command
A
BA
CK
CS
WE
REF
ADDRESS
BANK ADDRESS
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