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參數(shù)資料
| 型號： | GS4576S09L-25 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA144 |
| 封裝： | UBGA-144 |
| 文件頁數(shù)： | 49/64頁 |
| 文件大小： | 2691K |
| 代理商： | GS4576S09L-25 |
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Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
53/64
2011, GSI Technology
Test Data-In (TDI)
The TDI ball is used to serially input test instructions and data into the registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP Controller State Diagram. TDI is connected to the Most Significant Bit
(MSB) of any register (see the TAP Controller Block Diagram).
Test Data-Out (TDO)
The TDO output ball is used to serially clock test instructions and data out from the registers. The TDO output driver is only active
during the Shift-IR and Shift-DR TAP controller states. In all other states, the TDO pin is in a High-Z state. The output changes on
the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register (see the TAP Controller Block
Diagram).
TAP Controller
The TAP controller is a finite state machine that uses the state of the TMS pin at the rising edge of TCK to navigate through its
various modes of operation. The TAP controller state diagram can be seen in the TAP Controller State Diagram. Each state is
described in detail below.
Test-Logic-Reset
The test-logic-reset controller state is entered when TMS is held High for at least five consecutive rising edges of TCK. As long as
TMS remains High, the TAP controller will remain in the test-logic-reset state. The test logic is inactive during this state.
Run-Test/Idle
The run-test/idle is a controller state in between scan operations. This state can be maintained by holding TMS Low. From here
either the data register scan, or subsequently, the instruction register scan can be selected.
Select-DR-Scan
Select-DR-scan is a temporary controller state. All test data registers retain their previous state while here.
Capture-DR
The Capture-DR state is where the data is parallel-loaded into the test data registers. If the Boundary Scan Register is the currently
selected register, then the data currently on the pins is latched into the test data registers.
Shift-DR
Data is shifted serially through the data register while in this state. As new data is input through the TDI pin, data is shifted out of
the TDO pin.
Exit1-DR, Pause-DR, and Exit2-DR
The purpose of Exit1-DR is used to provide a path to return back to the run-test/idle state (through the Update-DR state). The
Pause-DR state is entered when the shifting of data through the test registers needs to be suspended. When shifting is to reconvene,
the controller enters the Exit2-DR state and then can re-enter the Shift-DR state.
Update-DR
When the EXTEST instruction is selected, there are latched parallel outputs of the boundary scan shift register that only change
state during the Update-DR controller state.
Instruction Register States
The instruction register states of the TAP controller are similar to the data register states. The desired instruction is serially shifted
into the instruction register during the Shift-IR state and is loaded during the Update-IR state.
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