參數(shù)資料
型號: GS4576S09L-25
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: DDR DRAM, PBGA144
封裝: UBGA-144
文件頁數(shù): 22/64頁
文件大?。?/td> 2691K
代理商: GS4576S09L-25
Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
29/64
2011, GSI Technology
Auto Refresh
The Auto Refresh (AREF) command launches a REFRESH cycle on one row in the bank addressed. Refresh row addresses are
generated by an internal refresh counter, so address inputs are Don’t Care, but a bank addresses (BA 2:0) must be provided during
the AREF command. A refresh may be contining in one bank while other commands, including other AREF commands, are
launched in other banks. The delay between the AREF command and a READ, WRITE or AREF command to the same bank must
be at least tRC.
The entire memory must be refreshed every 32 ms (tREF). This means that this 576Mb device requires 128K refresh cycles at an
average periodic interval of 0.24
μs MAX (actual periodic refresh interval is 32 ms/16K rows/8 = 0.244μs). To improve efficiency,
eight AREF commands (one for each bank) can be launched at periodic intervals of 1.95
μs (32 ms/16K rows = 1.95μs). The Auto
Refresh Cycle diagram illustrates an example of a refresh sequence.
Auto Refresh (AREF) Command
BA
CK
CS
WE
REF
ADDRESS
BANK ADDRESS
Auto Refresh Cycle
AREF
NOP
AREF
BA0
BA3
BA4
CK
CMD
Bank
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