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參數(shù)資料
| 型號： | GS4576S09L-25 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA144 |
| 封裝： | UBGA-144 |
| 文件頁數(shù)： | 29/64頁 |
| 文件大小： | 2691K |
| 代理商： | GS4576S09L-25 |
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Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
35/64
2011, GSI Technology
Write Command in Multiplexed Mode
Address Multiplexed Write data transfers are launched with a Write command, as shown below. A valid address must be provided
during the Write command. The Ax address must be loaded on the same true clock crossing used to load the Write command and
the Bank address. The Ay address and a NOP command must be provided at the next clock crossing.
During Write data transfers, each beat of incoming data is registered on crossings of DK and DK until the burst transfer is
complete. Write Latency (WL) is always one cycle longer than the programmed Read Latency (RL).
A Write burst may be followed by a Read command (assuming tRC is met). The Write-to-Read timing diagrams illustrate the
timing requirements for a Write followed by a Read. Setup and hold times for incoming D relative to the DK edges are specified as
t
DS and tDH. Input data may be masked high on an associated DM pin. The setup and hold times for the DM signal are tDS and
t
DH.
Write Command in Multiplexed Mode
WRITE
Ax
Ay
BA
CK
CS
WE
REF
ADDRESS
BANK ADDRESS
Write Burst Length 4, Configuration 1 in Multiplexed Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
BA0
BA1
BA0
BA3
BA0
D0a
D0b
D0c
D0d
D1a
D1b
WL = 6
RC = 4
CK
CMD
ADDR
BA
DK
DM
D
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