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參數(shù)資料
| 型號： | GS4576S09L-25 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA144 |
| 封裝： | UBGA-144 |
| 文件頁數(shù)： | 43/64頁 |
| 文件大?。?/td> | 2691K |
| 代理商： | GS4576S09L-25 |
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Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
48/64
2011, GSI Technology
Operating Burst Write Current
Example
BL= 2; Cyclic bank access; Half of address
bits change every clock cycle; Continuous
data; Measurement is taken during
continuous Write.
IDD2W (VDD) x9/x18
TBD
mA
IDD2W (VEXT)
TBD
Operating Burst Write Current
Example
BL= 4; Cyclic bank access; Half of address
bits change every two clock cycles;
Continuous data; Measurement is taken
during continuous Write.
IDD4W (VDD )x9/x18
TBD
mA
IDD4W (VEXT)
TBD
Operating Burst Write Current
Example
BL= 8; Cyclic bank access; Half of address
bits change every four clock cycles;
Continuous data; Measurement is taken
during continuous Write.
IDD8W (VDD) x9/x18
TBD
mA
IDD8W (VEXT)
TBD
Operating Burst Read
Current Example
BL= 2; Cyclic bank access; Half of address
bits change every clock cycle; Continuous
data; Measurement is taken during
continuous Read.
IDD2R (VDD)x9/x18
TBD
mA
IDD2R (VEXT)
TBD
Operating Burst Read
Current Example
BL= 4; Cyclic bank access; Half of address
bits change every two clock cycles;
Continuous data; Measurement is taken
during continuous Read.
IDD4R (VDD) x9/x18
TBD
mA
IDD4R (VEXT)
TBD
Operating Burst Read
Current Example
BL= 8; Cyclic bank access; Half of address
bits change every four clock cycles;
Continuous data; Measurement is taken
during continuous Read.
IDD8R (VDD) x9/x18
TBD
mA
IDD8R (VEXT)
TBD
Notes:
1. I
DD specifications are tested after the device is properly initialized and is operating at worst-case rated temperature and voltage specifications.
2.
Definitions of IDD Conditions:
3a. Low is defined as VIN
≤ VIL(AC) MAX.
3b. High is defined as VIN
> VIH(AC) MIN.
3c. Stable is defined as inputs remaining at a High or Low level.
3d. Floating is defined as inputs at VREF = VDDQ/2.
3e. Continuous data is defined as half the D or Q signals changng between High and Low every half clock cycle (twice per clock).
3f. Continuous address is defined as half the address signals changing between High and Low every clock cycles (once per clock).
3g. Sequential bank access is defined as the bank address incrementing by one every tRC.
3h. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL = 4 this
is every other clock, and for BL = 8 this is every fourth clock.
3.
CS is High unless a Read, Write, AREF, or MRS command is registered. CS never transitions more than once per clock cycle.
4. I
DD parameters are specified with ODT disabled.
5. Tests for AC timing, I
DD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operations are tested for the full voltage range specified.
6. I
DD tests may use a VIL-to-VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and
parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test
the device is 2 V/ns in the range between VIL(AC) andVIH(AC).
IDD Operating Conditions (Continued)
Description
Condition
Symbol
-18
-24
-25
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Un
its
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