參數(shù)資料
型號(hào)： GS4576S09L-25
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： DDR DRAM, PBGA144
封裝： UBGA-144
文件頁(yè)數(shù)： 44/64頁(yè)
文件大?。?/td> 2691K
代理商： GS4576S09L-25
Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
49/64
2011, GSI Technology
AC Electrical Characteristics
Parameter
Symbol
–18
–24
–25
–33
Uni
ts
Not
es
Min
Max
Min
Max
Min
Max
Min
Max
Clock
Input Clock Cycle Time
tCK
1.875
2.7
2.5
5.7
2.5
5.7
3.3
5.7
ns
—
Input data clock cycle time
tDK
tCK
ns
—
Clock jitter: period
tJITPER
–100
100
–150
150
–150
150
–200
200
ps
5, 6
Clock jitter: cycle-to-cycle
tJITCC
—
200
—
300
—
300
—
400
ps
—
Clock High Time
tCKH
tDKH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
—
Clock Low Time
tCKL
tDKL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
—
Clock to input data clock
tCKDK
–0.3
0.3
–0.45
0.5
–0.45
0.5
–0.45
1.2
ns
—
Mode register set cycle time
to any command
tMRSC
6
—
6
—
6
—
6
—
tCK
—
Setup Times
Address/command and input
setup time
tAS/tCS
0.3
—
0.4
—
0.4
—
0.5
—
ns
—
Data–in and data mask to
DK set up time
tDS
0.17
—
0.25
—
0.25
—
0.3
—
ns
—
Hold Times
Address/command and input
hold time
tAH/tCS
0.3
—
0.4
—
0.4
—
0.5
—
ns
—
Data-in and data mask to
DK setup time
tDH
0.17
—
0.25
—
0.25
—
0.3
—
ns
—
Data and Data Strobe
Output data clock High time
tQKH
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCKH
—
Output data clock Low time
tQKL
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCKL
—
Half–clock period
tQHP
MIN
(tQKH, tQKL)
—
MIN
(tQKH, tQKL)
—
MIN
(tQKH, tQKL)
—
MIN
(tQKH, tQKL)
—
QK edge to clock edge skew
tCKQK
–0.2
0.2
–0.25
0.25
–0.25
0.25
–0.3
0.3
ns
—
QK edge to output data
edge
tQKQ0,
tQKQ1
–0.12
0.12
–0.2
0.2
–0.2
0.2
–0.25
0.25
ns
7
QK edge to any output data
edge
tQKQ
–0.22
0.22
–0.3
0.3
–0.3
0.3
–0.35
0.35
ns
8
QK edge to QVLD
tQKVLD
–0.22
0.22
–0.3
0.3
–0.3
0.3
–0.35
0.35
ns
—
Data Valid Window
tDVW
tDVW (MIN)
—
tDVW (MIN)
—
tDVW (MIN)
—
tDVW (MIN)
—
9
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