參數(shù)資料
型號: GS4576S09L-25
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: DDR DRAM, PBGA144
封裝: UBGA-144
文件頁數(shù): 25/64頁
文件大?。?/td> 2691K
代理商: GS4576S09L-25
Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
31/64
2011, GSI Technology
Power-Up Multiplexed Address Mode
200us Min
tMRSC
Refresh 1024 NOP cycles Min
NOP
MRS
NOP
MRS
NOP
RF0
RF7
NOP
AC
CODE(1,2)
CODE(2,3)
Ax(2,4)
Ay(2)
Valid(5)
Bank 0
Bank 7
Valid(5)
tDKL
tDK
tDKL
tDKH
tDK
tCKL
tCK
tCKL
tCKH
tCK
VEXT
VDD
VDDQ
VREF
VTT
CK
DK
Command
ADDR
Bank
All Banks(9)
Notes:
1. Recommended that all address pins held Low during dummy MRS commands.
2. A10–A18 must be Low.
3. Set address A5 High. This enbles the part to enter Multiplexed Address mode when in Non-Multiplexed mode operation. Multiplexed
Address mode can also be entered at some later time by issuing an MRS command with A5 High. Once address Bit A5 is set High, tMRSC
must be satisfied before the two-cycle multiplexed mode MRS command is issued.
4. Address A5 must be set High. This and the following step set the desired mode register once the LLDRAM II is in Multiplexed Address
mode.
5. Any command or address.
6. The above sequence must be followed in order to power up the LLDRAM II in the Multiplexed Address mode.
7. DLL must be reset if tCK or VDD are changed.
8. CK and CK must separated at all times to prevent bogus commands from being issued.
9. The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP commands) does not matter. As is required for any
operation, tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank.
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